OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [or32/] [or32.S] - Diff between revs 154 and 242

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 154 Rev 242
Line 6... Line 6...
        .align 4        ;\
        .align 4        ;\
        .global symbol  ;\
        .global symbol  ;\
symbol:
symbol:
 
 
#ifdef L__mulsi3
#ifdef L__mulsi3
ENTRY(___mulsi3)
ENTRY(__mulsi3)
        l.addi r11,r0,0x0
        l.addi r11,r0,0x0
        l.sfne r3,r11
        l.sfne r3,r11
        l.bnf 3f
        l.bnf 3f
        l.ori r5,r3,0x0
        l.ori r5,r3,0x0
        l.addi r6,r0,0x0
        l.addi r6,r0,0x0
Line 28... Line 28...
        l.jr r9
        l.jr r9
        l.nop 0x0
        l.nop 0x0
#endif
#endif
 
 
#ifdef L__udivsi3
#ifdef L__udivsi3
ENTRY(___udivsi3)
ENTRY(__udivsi3)
        l.addi          r1,r1,-4
        l.addi          r1,r1,-4
        l.sw            0(r1),r9
        l.sw            0(r1),r9
        l.addi          r11,r0,0
        l.addi          r11,r0,0
        l.addi          r8,r4,0
        l.addi          r8,r4,0
        l.addi          r5,r3,0
        l.addi          r5,r3,0
Line 104... Line 104...
        l.addi          r1,r1,4
        l.addi          r1,r1,4
#endif
#endif
 
 
 
 
#ifdef L__divsi3
#ifdef L__divsi3
ENTRY(___divsi3)
ENTRY(__divsi3)
        l.addi          r1,r1,-8
        l.addi          r1,r1,-8
        l.sw            0(r1),r9
        l.sw            0(r1),r9
        l.sw            4(r1),r14
        l.sw            4(r1),r14
        l.addi          r5,r3,0
        l.addi          r5,r3,0
        l.addi          r14,r0,0
        l.addi          r14,r0,0
Line 122... Line 122...
        l.bnf           1f
        l.bnf           1f
        l.nop           0
        l.nop           0
        l.addi          r14,r14,1
        l.addi          r14,r14,1
        l.sub           r4,r0,r4
        l.sub           r4,r0,r4
1:
1:
        l.jal           ___udivsi3
        l.jal           __udivsi3
        l.addi          r3,r5,0
        l.addi          r3,r5,0
        l.sfeqi         r14,1
        l.sfeqi         r14,1
        l.bnf           1f
        l.bnf           1f
        l.nop           0
        l.nop           0
        l.sub           r11,r0,r11
        l.sub           r11,r0,r11
Line 137... Line 137...
        l.addi          r1,r1,8
        l.addi          r1,r1,8
#endif
#endif
 
 
 
 
#ifdef L__umodsi3
#ifdef L__umodsi3
ENTRY(___umodsi3)
ENTRY(__umodsi3)
        l.addi          r1,r1,-4
        l.addi          r1,r1,-4
        l.sw            0(r1),r9
        l.sw            0(r1),r9
        l.jal           ___udivsi3
        l.jal           __udivsi3
        l.nop           0
        l.nop           0
        l.addi          r11,r7,0
        l.addi          r11,r7,0
        l.lwz           r9,0(r1)
        l.lwz           r9,0(r1)
        l.jr            r9
        l.jr            r9
        l.addi          r1,r1,4
        l.addi          r1,r1,4
#endif
#endif
 
 
 
 
#ifdef L__modsi3
#ifdef L__modsi3
ENTRY(___modsi3)
ENTRY(__modsi3)
        l.addi          r1,r1,-8
        l.addi          r1,r1,-8
        l.sw            0(r1),r9
        l.sw            0(r1),r9
        l.sw            4(r1),r14
        l.sw            4(r1),r14
        l.addi          r14,r0,0
        l.addi          r14,r0,0
        l.sflts         r3,r0
        l.sflts         r3,r0
Line 166... Line 166...
        l.sflts         r4,r0
        l.sflts         r4,r0
        l.bnf           1f
        l.bnf           1f
        l.nop           0
        l.nop           0
        l.sub           r4,r0,r4
        l.sub           r4,r0,r4
1:
1:
        l.jal           ___udivsi3
        l.jal           __udivsi3
        l.nop           0
        l.nop           0
        l.sfeqi         r14,1
        l.sfeqi         r14,1
        l.bnf           1f
        l.bnf           1f
        l.addi          r11,r7,0
        l.addi          r11,r7,0
        l.sub           r11,r0,r11
        l.sub           r11,r0,r11

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.