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;; Machine description for GNU compiler, OpenRISC 1000 family, OR32 ISA
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;; Machine description for GNU compiler, OpenRISC 1000 family, OR32 ISA
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;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software
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;; Foundation, Inc.
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;; Contributed by Damjan Lampret in 1999.
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;; Contributed by Damjan Lampret in 1999.
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;; Major optimizations by Matjaz Breskvar in 2005.
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;; Major optimizations by Matjaz Breskvar in 2005.
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;; Floating point additions by Jungsook Yang and Julius Baxter
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;; Floating point additions by Jungsook Yang and
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;; Julius Baxter
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;; This file is part of GNU CC.
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;; This file is part of GNU CC.
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;; GNU CC is free software; you can redistribute it and/or modify
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;; GNU CC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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(define_attr "type"
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(define_attr "type"
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"unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp"
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"unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp"
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(const_string "unknown"))
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(const_string "unknown"))
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;; Number of instructions
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;; Number of machine instructions required to implement an insn.
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(define_attr "length" "" (const_int 1))
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(define_attr "length" "" (const_int 1))
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;; Single delay slot after branch or jump instructions, wich may contain any
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;; instruction but another branch or jump.
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(define_delay (eq_attr "type" "branch,jump")
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(define_delay (eq_attr "type" "branch,jump")
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[(and (eq_attr "type" "!branch,jump")
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[(and (eq_attr "type" "!branch,jump")
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(eq_attr "length" "1")) (nil) (nil)])
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(eq_attr "length" "1")) (nil) (nil)])
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;; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
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;; ALU is modelled as a single functional unit, which is reserved for varying
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;; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
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;; numbers of slots.
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;; MULTIPLICITY - Number of functional units of this type
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;; SIMULTANEITY - Zero for pipelined functional unit
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;; READY-DELAY - Number of cycles before result is available
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;; ISSUE-DELAY - Number of cycles before unit can accept new instruction
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;;
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;;
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;(define_function_unit "bit_unit" 1 0 (eq_attr "type" "shift") 3 1)
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;; I think this is all incorrect for the OR1K. The latency says when the
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;(define_function_unit "lsu" 1 0 (eq_attr "type" "load") 3 3)
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;; result will be ready, not how long the pipeline takes to execute.
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;(define_function_unit "lsu" 1 0 (eq_attr "type" "store") 2 1)
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;(define_function_unit "alu" 1 0 (eq_attr "type" "add,logic,extend,move,compare") 2 1)
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;(define_function_unit "mul_unit" 1 0 (eq_attr "type" "mul") 16 16)
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(define_cpu_unit "or32_alu")
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(define_cpu_unit "or32_alu")
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(define_insn_reservation "bit_unit" 3 (eq_attr "type" "shift") "or32_alu")
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(define_insn_reservation "bit_unit" 3 (eq_attr "type" "shift") "or32_alu")
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(define_insn_reservation "lsu_load" 3 (eq_attr "type" "load") "or32_alu*3")
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(define_insn_reservation "lsu_load" 3 (eq_attr "type" "load") "or32_alu*3")
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(define_insn_reservation "lsu_store" 2 (eq_attr "type" "store") "or32_alu")
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(define_insn_reservation "lsu_store" 2 (eq_attr "type" "store") "or32_alu")
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(define_insn_reservation "alu_unit" 2 (eq_attr "type" "add,logic,extend,move,compare") "or32_alu")
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(define_insn_reservation "alu_unit" 2
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(eq_attr "type" "add,logic,extend,move,compare")
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"or32_alu")
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(define_insn_reservation "mul_unit" 16 (eq_attr "type" "mul") "or32_alu*16")
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(define_insn_reservation "mul_unit" 16 (eq_attr "type" "mul") "or32_alu*16")
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;; Called after register allocation to add any instructions needed for the
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;; Called after register allocation to add any instructions needed for the
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;; prologue. Using a prologue insn is favored compared to putting all of the
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;; prologue. Using a prologue insn is favored compared to putting all of the
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