| Line 1... |
Line 1... |
;; Machine description for GNU compiler, OpenRISC 1000 family, OR32 ISA
|
;; Machine description for GNU compiler, OpenRISC 1000 family, OR32 ISA
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;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
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;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
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;; 2009, 2010 Free Software Foundation, Inc.
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;; 2009, 2010 Free Software Foundation, Inc.
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;; Copyright (C) 2010 Embecosm Limited
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|
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;; Contributed by Damjan Lampret in 1999.
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;; Contributed by Damjan Lampret in 1999.
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;; Major optimizations by Matjaz Breskvar in 2005.
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;; Major optimizations by Matjaz Breskvar in 2005.
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;; Floating point additions by Jungsook Yang
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;; Floating point additions by Jungsook Yang
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;; Julius Baxter in 2010
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;; Julius Baxter in 2010
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;; Updated for GCC 4.5 by Jeremy Bennett in 2010
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;; Updated for GCC 4.5 by Jeremy Bennett
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;; and Joern Rennecke in 2010
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|
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;; This file is part of GNU CC.
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;; This file is part of GNU CC.
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|
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;; This program is free software; you can redistribute it and/or modify it
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;; This program is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by the Free
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;; under the terms of the GNU General Public License as published by the Free
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| Line 21... |
Line 23... |
;; more details.
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;; more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License along
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;; You should have received a copy of the GNU General Public License along
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;; with this program. If not, see . */
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;; with this program. If not, see . */
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|
|
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(define_constants [
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(CC_REG 34)
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|
|
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;; unspec_volatile values
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(UNSPECV_SIBCALL_EPILOGUE 0)
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|
])
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|
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(include "predicates.md")
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(include "predicates.md")
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|
|
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(include "constraints.md")
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|
|
(define_attr "type"
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(define_attr "type"
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"unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp"
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"unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp,jump_restore"
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(const_string "unknown"))
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(const_string "unknown"))
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|
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;; Number of machine instructions required to implement an insn.
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;; Number of machine instructions required to implement an insn.
|
(define_attr "length" "" (const_int 1))
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(define_attr "length" "" (const_int 1))
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|
|
| Line 60... |
Line 71... |
;; some cases, it might be necessary to emit a barrier instruction as the last
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;; some cases, it might be necessary to emit a barrier instruction as the last
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;; insn to prevent such scheduling.
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;; insn to prevent such scheduling.
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|
|
(define_expand "prologue"
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(define_expand "prologue"
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[(use (const_int 1))]
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[(use (const_int 1))]
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"TARGET_MASK_SCHED_LOGUE"
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"TARGET_SCHED_LOGUE"
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{
|
{
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or32_expand_prologue ();
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or32_expand_prologue ();
|
DONE;
|
DONE;
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})
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})
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|
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| Line 74... |
Line 85... |
;; to intermix instructions with the restores of the caller saved registers.
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;; to intermix instructions with the restores of the caller saved registers.
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;; In some cases, it might be necessary to emit a barrier instruction as the
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;; In some cases, it might be necessary to emit a barrier instruction as the
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;; first insn to prevent such scheduling.
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;; first insn to prevent such scheduling.
|
(define_expand "epilogue"
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(define_expand "epilogue"
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[(use (const_int 2))]
|
[(use (const_int 2))]
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"TARGET_MASK_SCHED_LOGUE"
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"TARGET_SCHED_LOGUE"
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{
|
{
|
or32_expand_epilogue (false);
|
or32_expand_epilogue (NULL_RTX);
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DONE;
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DONE;
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})
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})
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|
|
(define_expand "sibcall_epilogue"
|
(define_insn_and_split "sibcall_epilogue"
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[(use (const_int 2))]
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[(unspec_volatile [(const_int 2)] UNSPECV_SIBCALL_EPILOGUE)]
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"TARGET_MASK_SCHED_LOGUE"
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"TARGET_SCHED_LOGUE"
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|
"#"
|
|
""
|
|
[(pc)]
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{
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{
|
or32_expand_epilogue (true);
|
or32_expand_epilogue (curr_insn);
|
DONE;
|
DONE;
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})
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})
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|
|
(define_insn "return_internal"
|
(define_insn "return_internal"
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[(return)
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[(return)
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(use (match_operand 0 "pmode_register_operand" ""))]
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(use (match_operand 0 "pmode_register_operand" ""))]
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"TARGET_MASK_SCHED_LOGUE"
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"TARGET_SCHED_LOGUE"
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"l.jr \t%0%("
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"l.jr \t%0%("
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[(set_attr "type" "jump")
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[(set_attr "type" "jump")
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(set_attr "length" "1")])
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(set_attr "length" "1")])
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|
|
;;
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;;
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| Line 105... |
Line 119... |
(define_expand "sibcall"
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(define_expand "sibcall"
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[(parallel [(call (match_operand 0 "" "")
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[(parallel [(call (match_operand 0 "" "")
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(match_operand 1 "" ""))
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(match_operand 1 "" ""))
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(use (match_operand 2 "" "")) ;; next_arg_reg
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(use (match_operand 2 "" "")) ;; next_arg_reg
|
(use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
|
(use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
|
"TARGET_MASK_SIBCALL"
|
""
|
"
|
"
|
{
|
{
|
or32_expand_sibcall (0, XEXP (operands[0], 0), operands[1]);
|
or32_expand_sibcall (0, XEXP (operands[0], 0), operands[1]);
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_expand "sibcall_value"
|
(define_expand "sibcall_value"
|
[(set (match_operand 0 "" "")
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[(set (match_operand 0 "" "")
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(call (match_operand:SI 1 "" "")
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(call (match_operand:SI 1 "" "")
|
(match_operand 2 "" "")))]
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(match_operand 2 "" "")))]
|
"TARGET_MASK_SIBCALL"
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""
|
"
|
"
|
{
|
{
|
or32_expand_sibcall (operands[0], XEXP (operands[1], 0), operands[2]);
|
or32_expand_sibcall (operands[0], XEXP (operands[1], 0), operands[2]);
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "sibcall_internal"
|
(define_insn "sibcall_internal"
|
[(call (mem:SI (match_operand:SI 0 "sibcall_insn_operand" "s,r"))
|
[(call (mem:SI (match_operand:SI 0 "sibcall_insn_operand" "s,Rsc,r"))
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(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(use (reg:SI 9))]
|
(use (reg:SI 9))]
|
"TARGET_MASK_SIBCALL"
|
""
|
"@
|
"@
|
l.j \t%S0%(\t # sibcall s
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l.j \t%S0%(\t # sibcall s
|
l.jr \t%0%(\t # sibcall r"
|
l.jr\t%0%(\t# sibcall Rsc
|
[(set_attr "type" "jump,jump")])
|
l.jr\t%0\t\t# sibcall r%J0"
|
|
[(set_attr "type" "jump,jump,jump_restore")])
|
|
|
|
|
|
|
;;
|
;;
|
;; movQI
|
;; movQI
|
| Line 285... |
Line 300... |
l.lwz \t%0,%1\t # SI load
|
l.lwz \t%0,%1\t # SI load
|
l.sw \t%0,%1\t # SI store"
|
l.sw \t%0,%1\t # SI store"
|
[(set_attr "type" "add,load,store,add,logic,move")
|
[(set_attr "type" "add,load,store,add,logic,move")
|
(set_attr "length" "1,1,1,1,1,1")])
|
(set_attr "length" "1,1,1,1,1,1")])
|
|
|
(define_insn "*movsi_lo_sum"
|
(define_insn "movsi_lo_sum"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
|
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
|
(match_operand:SI 2 "immediate_operand" "i")))]
|
(match_operand:SI 2 "immediate_operand" "i")))]
|
""
|
""
|
"l.ori \t%0,%1,lo(%2)"
|
"l.ori \t%0,%1,lo(%2)"
|
[(set_attr "type" "logic")
|
[(set_attr "type" "logic")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "*movsi_high"
|
(define_insn "movsi_high"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(high:SI (match_operand:SI 1 "immediate_operand" "i")))]
|
(high:SI (match_operand:SI 1 "immediate_operand" "i")))]
|
""
|
""
|
"l.movhi \t%0,hi(%1)"
|
"l.movhi \t%0,hi(%1)"
|
[(set_attr "type" "move")
|
[(set_attr "type" "move")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "movsi_insn_big"
|
(define_insn_and_split "movsi_insn_big"
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(match_operand:SI 1 "immediate_operand" "i"))]
|
(match_operand:SI 1 "immediate_operand" "i"))]
|
"GET_CODE(operands[1]) != CONST_INT"
|
"GET_CODE(operands[1]) != CONST_INT"
|
"l.movhi \t%0,hi(%1)\;l.ori \t%0,%0,lo(%1)"
|
"l.movhi \t%0,hi(%1)\;l.ori \t%0,%0,lo(%1)"
|
|
;; the switch of or32 bfd to Rela allows us to schedule insns separately.
|
|
"&& reload_completed
|
|
&& GET_CODE (operands[1]) != HIGH && GET_CODE (operands[1]) != LO_SUM"
|
|
[(pc)]
|
|
{
|
|
emit_insn (gen_movsi_high (operands[0], operands[1]));
|
|
emit_insn (gen_movsi_lo_sum (operands[0], operands[0], operands[1]));
|
|
DONE;
|
|
}
|
[(set_attr "type" "move")
|
[(set_attr "type" "move")
|
(set_attr "length" "2")])
|
(set_attr "length" "2")])
|
|
|
|
|
;;
|
;;
|
| Line 430... |
Line 454... |
|
|
;; JPB 31-Aug-10: cmpxx appears to be obsolete in GCC 4.5. Needs more
|
;; JPB 31-Aug-10: cmpxx appears to be obsolete in GCC 4.5. Needs more
|
;; investigation.
|
;; investigation.
|
|
|
;;(define_expand "cmpsi"
|
;;(define_expand "cmpsi"
|
;; [(set (reg:CC 32)
|
;; [(set (reg:CC CC_REG)
|
;; (compare:CC (match_operand:SI 0 "register_operand" "")
|
;; (compare:CC (match_operand:SI 0 "register_operand" "")
|
;; (match_operand:SI 1 "nonmemory_operand" "")))]
|
;; (match_operand:SI 1 "nonmemory_operand" "")))]
|
;; ""
|
;; ""
|
;; {
|
;; {
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
| Line 443... |
Line 467... |
;; or32_compare_op1 = operands[1];
|
;; or32_compare_op1 = operands[1];
|
;; DONE;
|
;; DONE;
|
;; })
|
;; })
|
|
|
;; (define_expand "cmpsf"
|
;; (define_expand "cmpsf"
|
;; [(set (reg:CC 32)
|
;; [(set (reg:CC CC_REG)
|
;; (compare:CC (match_operand:SF 0 "register_operand" "")
|
;; (compare:CC (match_operand:SF 0 "register_operand" "")
|
;; (match_operand:SF 1 "register_operand" "")))]
|
;; (match_operand:SF 1 "register_operand" "")))]
|
;; "TARGET_HARD_FLOAT"
|
;; "TARGET_HARD_FLOAT"
|
;; {
|
;; {
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
| Line 485... |
Line 509... |
|
|
|
|
|
|
;; Here are the actual compare insns.
|
;; Here are the actual compare insns.
|
(define_insn "*cmpsi_eq"
|
(define_insn "*cmpsi_eq"
|
[(set (reg:CCEQ 32)
|
[(set (reg:CCEQ CC_REG)
|
(compare:CCEQ (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCEQ (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfeqi\t%0,%1
|
l.sfeqi\t%0,%1
|
l.sfeq \t%0,%1")
|
l.sfeq \t%0,%1")
|
|
|
(define_insn "*cmpsi_ne"
|
(define_insn "*cmpsi_ne"
|
[(set (reg:CCNE 32)
|
[(set (reg:CCNE CC_REG)
|
(compare:CCNE (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCNE (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfnei\t%0,%1
|
l.sfnei\t%0,%1
|
l.sfne \t%0,%1")
|
l.sfne \t%0,%1")
|
|
|
(define_insn "*cmpsi_gt"
|
(define_insn "*cmpsi_gt"
|
[(set (reg:CCGT 32)
|
[(set (reg:CCGT CC_REG)
|
(compare:CCGT (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCGT (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfgtsi\t%0,%1
|
l.sfgtsi\t%0,%1
|
l.sfgts \t%0,%1")
|
l.sfgts \t%0,%1")
|
|
|
(define_insn "*cmpsi_gtu"
|
(define_insn "*cmpsi_gtu"
|
[(set (reg:CCGTU 32)
|
[(set (reg:CCGTU CC_REG)
|
(compare:CCGTU (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCGTU (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfgtui\t%0,%1
|
l.sfgtui\t%0,%1
|
l.sfgtu \t%0,%1")
|
l.sfgtu \t%0,%1")
|
|
|
(define_insn "*cmpsi_lt"
|
(define_insn "*cmpsi_lt"
|
[(set (reg:CCLT 32)
|
[(set (reg:CCLT CC_REG)
|
(compare:CCLT (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCLT (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfltsi\t%0,%1
|
l.sfltsi\t%0,%1
|
l.sflts \t%0,%1")
|
l.sflts \t%0,%1")
|
|
|
(define_insn "*cmpsi_ltu"
|
(define_insn "*cmpsi_ltu"
|
[(set (reg:CCLTU 32)
|
[(set (reg:CCLTU CC_REG)
|
(compare:CCLTU (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCLTU (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfltui\t%0,%1
|
l.sfltui\t%0,%1
|
l.sfltu \t%0,%1")
|
l.sfltu \t%0,%1")
|
|
|
(define_insn "*cmpsi_ge"
|
(define_insn "*cmpsi_ge"
|
[(set (reg:CCGE 32)
|
[(set (reg:CCGE CC_REG)
|
(compare:CCGE (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCGE (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfgesi\t%0,%1
|
l.sfgesi\t%0,%1
|
l.sfges \t%0,%1")
|
l.sfges \t%0,%1")
|
|
|
|
|
(define_insn "*cmpsi_geu"
|
(define_insn "*cmpsi_geu"
|
[(set (reg:CCGEU 32)
|
[(set (reg:CCGEU CC_REG)
|
(compare:CCGEU (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCGEU (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfgeui\t%0,%1
|
l.sfgeui\t%0,%1
|
l.sfgeu \t%0,%1")
|
l.sfgeu \t%0,%1")
|
|
|
|
|
(define_insn "*cmpsi_le"
|
(define_insn "*cmpsi_le"
|
[(set (reg:CCLE 32)
|
[(set (reg:CCLE CC_REG)
|
(compare:CCLE (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCLE (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sflesi\t%0,%1
|
l.sflesi\t%0,%1
|
l.sfles \t%0,%1")
|
l.sfles \t%0,%1")
|
|
|
(define_insn "*cmpsi_leu"
|
(define_insn "*cmpsi_leu"
|
[(set (reg:CCLEU 32)
|
[(set (reg:CCLEU CC_REG)
|
(compare:CCLEU (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCLEU (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfleui\t%0,%1
|
l.sfleui\t%0,%1
|
l.sfleu \t%0,%1")
|
l.sfleu \t%0,%1")
|
|
|
;; Single precision floating point evaluation instructions
|
;; Single precision floating point evaluation instructions
|
(define_insn "*cmpsf_eq"
|
(define_insn "*cmpsf_eq"
|
[(set (reg:CCEQ 32)
|
[(set (reg:CCEQ CC_REG)
|
(compare:CCEQ (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCEQ (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfeq.s\t%0,%1")
|
"lf.sfeq.s\t%0,%1")
|
|
|
(define_insn "*cmpsf_ne"
|
(define_insn "*cmpsf_ne"
|
[(set (reg:CCNE 32)
|
[(set (reg:CCNE CC_REG)
|
(compare:CCNE (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCNE (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfne.s\t%0,%1")
|
"lf.sfne.s\t%0,%1")
|
|
|
|
|
(define_insn "*cmpsf_gt"
|
(define_insn "*cmpsf_gt"
|
[(set (reg:CCGT 32)
|
[(set (reg:CCGT CC_REG)
|
(compare:CCGT (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCGT (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfgt.s\t%0,%1")
|
"lf.sfgt.s\t%0,%1")
|
|
|
(define_insn "*cmpsf_ge"
|
(define_insn "*cmpsf_ge"
|
[(set (reg:CCGE 32)
|
[(set (reg:CCGE CC_REG)
|
(compare:CCGE (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCGE (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfge.s\t%0,%1")
|
"lf.sfge.s\t%0,%1")
|
|
|
|
|
(define_insn "*cmpsf_lt"
|
(define_insn "*cmpsf_lt"
|
[(set (reg:CCLT 32)
|
[(set (reg:CCLT CC_REG)
|
(compare:CCLT (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCLT (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sflt.s\t%0,%1")
|
"lf.sflt.s\t%0,%1")
|
|
|
(define_insn "*cmpsf_le"
|
(define_insn "*cmpsf_le"
|
[(set (reg:CCLE 32)
|
[(set (reg:CCLE CC_REG)
|
(compare:CCLE (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCLE (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfle.s\t%0,%1")
|
"lf.sfle.s\t%0,%1")
|
|
|
| Line 987... |
Line 1011... |
[(set (pc)
|
[(set (pc)
|
(label_ref (match_operand 0 "" "")))]
|
(label_ref (match_operand 0 "" "")))]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
|
emit_jump_insn (gen_jump_internal (operands[0]));
|
emit_jump_insn (gen_jump_internal (operands[0]));
|
else
|
|
emit_jump_insn (gen_jump_aligned (operands[0]));
|
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "jump_internal"
|
(define_insn "jump_internal"
|
[(set (pc)
|
[(set (pc)
|
(label_ref (match_operand 0 "" "")))]
|
(label_ref (match_operand 0 "" "")))]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
""
|
"l.j \t%l0%("
|
"l.j \t%l0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "jump_aligned"
|
|
[(set (pc)
|
|
(label_ref (match_operand 0 "" "")))]
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
|
".balignl 0x8,0x15000015,0x4\;l.j \t%l0%("
|
|
[(set_attr "type" "jump")
|
|
(set_attr "length" "1")])
|
|
|
|
;; indirect jump
|
;; indirect jump
|
|
|
(define_expand "indirect_jump"
|
(define_expand "indirect_jump"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
|
emit_jump_insn (gen_indirect_jump_internal (operands[0]));
|
emit_jump_insn (gen_indirect_jump_internal (operands[0]));
|
else
|
|
emit_jump_insn (gen_indirect_jump_aligned (operands[0]));
|
|
DONE;
|
DONE;
|
|
|
}")
|
}")
|
|
|
(define_insn "indirect_jump_internal"
|
(define_insn "indirect_jump_internal"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
""
|
"l.jr \t%0%("
|
"l.jr \t%0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "indirect_jump_aligned"
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
|
".balignl 0x8,0x15000015,0x4\;l.jr \t%0%("
|
|
[(set_attr "type" "jump")
|
|
(set_attr "length" "1")])
|
|
|
|
;;
|
;;
|
;; calls
|
;; calls
|
;;
|
;;
|
|
|
;; call
|
;; call
|
| Line 1052... |
Line 1055... |
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
|
emit_call_insn (gen_call_internal (operands[0], operands[1]));
|
emit_call_insn (gen_call_internal (operands[0], operands[1]));
|
else
|
|
emit_call_insn (gen_call_aligned (operands[0], operands[1]));
|
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "call_internal"
|
(define_insn "call_internal"
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
""
|
"l.jal \t%S0%("
|
"l.jal \t%S0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "call_aligned"
|
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
|
(match_operand 1 "" "i"))
|
|
(clobber (reg:SI 9))])]
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
|
".balignl 0x8,0x15000015,0x4\;l.jal \t%S0%("
|
|
[(set_attr "type" "jump")
|
|
(set_attr "length" "1")])
|
|
|
|
;; call value
|
;; call value
|
|
|
(define_expand "call_value"
|
(define_expand "call_value"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
|
emit_call_insn (gen_call_value_internal (operands[0], operands[1], operands[2]));
|
emit_call_insn (gen_call_value_internal (operands[0], operands[1], operands[2]));
|
else
|
|
emit_call_insn (gen_call_value_aligned (operands[0], operands[1], operands[2]));
|
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "call_value_internal"
|
(define_insn "call_value_internal"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
""
|
"l.jal \t%S1%("
|
"l.jal \t%S1%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "call_value_aligned"
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
|
(match_operand 2 "" "i")))
|
|
(clobber (reg:SI 9))])]
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
|
".balignl 0x8,0x15000015,0x4\;l.jal \t%S1%("
|
|
[(set_attr "type" "jump")
|
|
(set_attr "length" "1")])
|
|
|
|
;; indirect call value
|
;; indirect call value
|
|
|
(define_expand "call_value_indirect"
|
(define_expand "call_value_indirect"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
|
emit_call_insn (gen_call_value_indirect_internal (operands[0], operands[1], operands[2]));
|
emit_call_insn (gen_call_value_indirect_internal (operands[0], operands[1], operands[2]));
|
else
|
|
emit_call_insn (gen_call_value_indirect_aligned (operands[0], operands[1], operands[2]));
|
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "call_value_indirect_internal"
|
(define_insn "call_value_indirect_internal"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
""
|
"l.jalr \t%1%("
|
"l.jalr \t%1%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "call_value_indirect_aligned"
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
|
(match_operand 2 "" "i")))
|
|
(clobber (reg:SI 9))])]
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
|
".balignl 0x8,0x15000015,0x4\;l.jalr \t%1%("
|
|
[(set_attr "type" "jump")
|
|
(set_attr "length" "1")])
|
|
|
|
;; indirect call
|
;; indirect call
|
|
|
(define_expand "call_indirect"
|
(define_expand "call_indirect"
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
|
emit_call_insn (gen_call_indirect_internal (operands[0], operands[1]));
|
emit_call_insn (gen_call_indirect_internal (operands[0], operands[1]));
|
else
|
|
emit_call_insn (gen_call_indirect_aligned (operands[0], operands[1]));
|
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "call_indirect_internal"
|
(define_insn "call_indirect_internal"
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
""
|
"l.jalr \t%0%("
|
"l.jalr \t%0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "call_indirect_aligned"
|
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
|
(match_operand 1 "" "i"))
|
|
(clobber (reg:SI 9))])]
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
|
".balignl 0x8,0x15000015,0x4\;l.jalr \t%0%("
|
|
[(set_attr "type" "jump")
|
|
(set_attr "length" "1")])
|
|
|
|
;; table jump
|
;; table jump
|
|
|
(define_expand "tablejump"
|
(define_expand "tablejump"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
if (CASE_VECTOR_PC_RELATIVE || flag_pic)
|
|
operands[0]
|
|
= force_reg (Pmode,
|
|
gen_rtx_PLUS (Pmode, operands[0],
|
|
gen_rtx_LABEL_REF (Pmode, operands[1])));
|
emit_jump_insn (gen_tablejump_internal (operands[0], operands[1]));
|
emit_jump_insn (gen_tablejump_internal (operands[0], operands[1]));
|
else
|
|
emit_jump_insn (gen_tablejump_aligned (operands[0], operands[1]));
|
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "tablejump_internal"
|
(define_insn "tablejump_internal"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
""
|
"l.jr \t%0%("
|
"l.jr \t%0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "tablejump_aligned"
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
|
(use (label_ref (match_operand 1 "" "")))]
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
|
".balignl 0x8,0x15000015,0x4\;l.jr \t%0%("
|
|
[(set_attr "type" "jump")
|
|
(set_attr "length" "1")])
|
|
|
|
|
|
;; no-op
|
;; no-op
|
|
|
(define_insn "nop"
|
(define_insn "nop"
|
[(const_int 0)]
|
[(const_int 0)]
|
