| Line 22... |
Line 22... |
;; This code iterator allows all branch instructions to
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;; This code iterator allows all branch instructions to
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;; be generated from a single define_expand template.
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;; be generated from a single define_expand template.
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(define_code_iterator most_cond [eq ne gt ge lt le gtu geu ltu leu
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(define_code_iterator most_cond [eq ne gt ge lt le gtu geu ltu leu
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unordered ordered ])
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unordered ordered ])
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;; Likewise, but only the ones that use Z or S.
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(define_code_iterator zs_cond [eq ne gtu geu ltu leu ])
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;; This code iterator is used for sign- and zero- extensions.
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;; This code iterator is used for sign- and zero- extensions.
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(define_mode_iterator small_int_modes [(HI "") (QI "")])
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(define_mode_iterator small_int_modes [(HI "") (QI "")])
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;; We do not handle DFmode here because it is either
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;; We do not handle DFmode here because it is either
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;; the same as SFmode, or if -m64bit-doubles is active
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;; the same as SFmode, or if -m64bit-doubles is active
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| Line 155... |
Line 158... |
;; pass has completed. That would be problematical because reload can
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;; pass has completed. That would be problematical because reload can
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;; generate ADDSI3 instructions which would corrupt the PSW flags.
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;; generate ADDSI3 instructions which would corrupt the PSW flags.
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(define_expand "cbranchsi4"
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(define_expand "cbranchsi4"
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[(set (pc)
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[(set (pc)
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(if_then_else (match_operator:SI 0 "comparison_operator"
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(if_then_else (match_operator 0 "comparison_operator"
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[(match_operand:SI 1 "register_operand")
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[(match_operand:SI 1 "register_operand")
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(match_operand:SI 2 "rx_source_operand")])
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(match_operand:SI 2 "rx_source_operand")])
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(label_ref (match_operand 3 ""))
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(label_ref (match_operand 3 ""))
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(pc)))
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(pc)))
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]
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]
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| Line 167... |
Line 170... |
""
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""
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)
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)
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(define_insn_and_split "*cbranchsi4_"
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(define_insn_and_split "*cbranchsi4_"
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[(set (pc)
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[(set (pc)
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(if_then_else (most_cond:SI (match_operand:SI 0 "register_operand" "r")
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(if_then_else (most_cond (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "rx_source_operand" "riQ"))
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(match_operand:SI 1 "rx_source_operand" "riQ"))
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(label_ref (match_operand 2 "" ""))
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(label_ref (match_operand 2 "" ""))
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(pc)))
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(pc)))
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]
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]
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""
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""
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| Line 187... |
Line 190... |
gen_rtx_fmt_ee (, CCmode,
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gen_rtx_fmt_ee (, CCmode,
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gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
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gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
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"
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"
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)
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)
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;; -----------------------------------------------------------------------------
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;; These two are the canonical TST/branch insns. However, GCC
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;; generates a wide variety of tst-like patterns, we catch those
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;; below.
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(define_insn_and_split "*tstbranchsi4_"
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[(set (pc)
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(if_then_else (zs_cond (and:SI (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "rx_source_operand" "riQ"))
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(const_int 0))
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(label_ref (match_operand 2 "" ""))
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(pc)))
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]
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""
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"#"
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"reload_completed"
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[(const_int 0)]
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"
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emit_insn (gen_tstsi (operands[0], operands[1]));
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emit_jump_insn (gen_conditional_branch (operands[2],
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gen_rtx_fmt_ee (, CCmode,
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gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
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"
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)
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;; Inverse of above
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(define_insn_and_split "*tstbranchsi4_"
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[(set (pc)
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(if_then_else (zs_cond (and:SI (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "rx_source_operand" "riQ"))
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(const_int 0))
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(pc)
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(label_ref (match_operand 2 "" ""))))
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]
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""
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"#"
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"reload_completed"
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[(const_int 0)]
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"
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emit_insn (gen_tstsi (operands[0], operands[1]));
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emit_jump_insn (gen_conditional_branch (operands[2],
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gen_rtx_fmt_ee (reverse_condition (), CCmode,
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gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
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"
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)
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;; Various other ways that GCC codes "var & const"
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(define_insn_and_split "*tstbranchsi4m_eq"
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[(set (pc)
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(if_then_else (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
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(match_operand 1 "rx_constshift_operand" "i")
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(match_operand 2 "rx_constshift_operand" "i"))
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(const_int 0))
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(label_ref (match_operand 3 "" ""))
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(pc)))
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]
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""
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"#"
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""
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[(set (pc)
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(if_then_else (eq (and:SI (match_dup 0)
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(match_dup 4))
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(const_int 0))
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(label_ref (match_dup 3))
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(pc)))
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]
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"operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));"
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)
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(define_insn_and_split "*tstbranchsi4m_ne"
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[(set (pc)
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(if_then_else (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
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(match_operand 1 "rx_constshift_operand" "i")
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(match_operand 2 "rx_constshift_operand" "i"))
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(const_int 0))
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(label_ref (match_operand 3 "" ""))
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(pc)))
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]
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""
|
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"#"
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""
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[(set (pc)
|
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(if_then_else (ne (and:SI (match_dup 0)
|
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(match_dup 4))
|
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(const_int 0))
|
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(label_ref (match_dup 3))
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(pc)))
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]
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"operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));"
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)
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;; -----------------------------------------------------------------------------
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|
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(define_expand "cbranchsf4"
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(define_expand "cbranchsf4"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (match_operator:SF 0 "comparison_operator"
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(if_then_else (match_operator 0 "comparison_operator"
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[(match_operand:SF 1 "register_operand")
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[(match_operand:SF 1 "register_operand")
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(match_operand:SF 2 "rx_source_operand")])
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(match_operand:SF 2 "rx_source_operand")])
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(label_ref (match_operand 3 ""))
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(label_ref (match_operand 3 ""))
|
(pc)))
|
(pc)))
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]
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]
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| Line 201... |
Line 299... |
""
|
""
|
)
|
)
|
|
|
(define_insn_and_split "*cbranchsf4_"
|
(define_insn_and_split "*cbranchsf4_"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (most_cond:SF (match_operand:SF 0 "register_operand" "r")
|
(if_then_else (most_cond (match_operand:SF 0 "register_operand" "r")
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(match_operand:SF 1 "rx_source_operand" "rFiQ"))
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(match_operand:SF 1 "rx_source_operand" "rFiQ"))
|
(label_ref (match_operand 2 "" ""))
|
(label_ref (match_operand 2 "" ""))
|
(pc)))
|
(pc)))
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]
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]
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"ALLOW_RX_FPU_INSNS"
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"ALLOW_RX_FPU_INSNS"
|
