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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [rx/] [rx.md] - Diff between revs 282 and 378

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Rev 282 Rev 378
Line 22... Line 22...
;; This code iterator allows all branch instructions to
;; This code iterator allows all branch instructions to
;; be generated from a single define_expand template.
;; be generated from a single define_expand template.
(define_code_iterator most_cond [eq ne gt ge lt le gtu geu ltu leu
(define_code_iterator most_cond [eq ne gt ge lt le gtu geu ltu leu
                                 unordered ordered ])
                                 unordered ordered ])
 
 
 
;; Likewise, but only the ones that use Z or S.
 
(define_code_iterator zs_cond [eq ne gtu geu ltu leu ])
 
 
;; This code iterator is used for sign- and zero- extensions.
;; This code iterator is used for sign- and zero- extensions.
(define_mode_iterator small_int_modes [(HI "") (QI "")])
(define_mode_iterator small_int_modes [(HI "") (QI "")])
 
 
;; We do not handle DFmode here because it is either
;; We do not handle DFmode here because it is either
;; the same as SFmode, or if -m64bit-doubles is active
;; the same as SFmode, or if -m64bit-doubles is active
Line 155... Line 158...
;; pass has completed.  That would be problematical because reload can
;; pass has completed.  That would be problematical because reload can
;; generate ADDSI3 instructions which would corrupt the PSW flags.
;; generate ADDSI3 instructions which would corrupt the PSW flags.
 
 
(define_expand "cbranchsi4"
(define_expand "cbranchsi4"
  [(set (pc)
  [(set (pc)
        (if_then_else (match_operator:SI 0 "comparison_operator"
        (if_then_else (match_operator 0 "comparison_operator"
                                         [(match_operand:SI 1 "register_operand")
                                         [(match_operand:SI 1 "register_operand")
                                          (match_operand:SI 2 "rx_source_operand")])
                                          (match_operand:SI 2 "rx_source_operand")])
                      (label_ref (match_operand 3 ""))
                      (label_ref (match_operand 3 ""))
                      (pc)))
                      (pc)))
   ]
   ]
Line 167... Line 170...
  ""
  ""
)
)
 
 
(define_insn_and_split "*cbranchsi4_"
(define_insn_and_split "*cbranchsi4_"
  [(set (pc)
  [(set (pc)
        (if_then_else (most_cond:SI (match_operand:SI  0 "register_operand"  "r")
        (if_then_else (most_cond (match_operand:SI  0 "register_operand"  "r")
                                    (match_operand:SI  1 "rx_source_operand" "riQ"))
                                    (match_operand:SI  1 "rx_source_operand" "riQ"))
                      (label_ref (match_operand        2 "" ""))
                      (label_ref (match_operand        2 "" ""))
                      (pc)))
                      (pc)))
   ]
   ]
  ""
  ""
Line 187... Line 190...
                 gen_rtx_fmt_ee (, CCmode,
                 gen_rtx_fmt_ee (, CCmode,
                                 gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
                                 gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
  "
  "
)
)
 
 
 
;; -----------------------------------------------------------------------------
 
;; These two are the canonical TST/branch insns.  However, GCC
 
;; generates a wide variety of tst-like patterns, we catch those
 
;; below.
 
(define_insn_and_split "*tstbranchsi4_"
 
  [(set (pc)
 
        (if_then_else (zs_cond (and:SI (match_operand:SI  0 "register_operand"  "r")
 
                                       (match_operand:SI  1 "rx_source_operand" "riQ"))
 
                               (const_int 0))
 
                      (label_ref (match_operand 2 "" ""))
 
                      (pc)))
 
   ]
 
  ""
 
  "#"
 
  "reload_completed"
 
  [(const_int 0)]
 
  "
 
  emit_insn (gen_tstsi (operands[0], operands[1]));
 
 
 
  emit_jump_insn (gen_conditional_branch (operands[2],
 
                 gen_rtx_fmt_ee (, CCmode,
 
                                 gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
 
  "
 
)
 
 
 
;; Inverse of above
 
(define_insn_and_split "*tstbranchsi4_"
 
  [(set (pc)
 
        (if_then_else (zs_cond (and:SI (match_operand:SI  0 "register_operand"  "r")
 
                                       (match_operand:SI  1 "rx_source_operand" "riQ"))
 
                               (const_int 0))
 
                      (pc)
 
                      (label_ref (match_operand 2 "" ""))))
 
   ]
 
  ""
 
  "#"
 
  "reload_completed"
 
  [(const_int 0)]
 
  "
 
  emit_insn (gen_tstsi (operands[0], operands[1]));
 
 
 
  emit_jump_insn (gen_conditional_branch (operands[2],
 
                 gen_rtx_fmt_ee (reverse_condition (), CCmode,
 
                                 gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
 
  "
 
)
 
 
 
;; Various other ways that GCC codes "var & const"
 
 
 
(define_insn_and_split "*tstbranchsi4m_eq"
 
  [(set (pc)
 
        (if_then_else (eq (zero_extract:SI (match_operand:SI  0 "register_operand"  "r")
 
                                           (match_operand  1 "rx_constshift_operand" "i")
 
                                           (match_operand  2 "rx_constshift_operand" "i"))
 
                          (const_int 0))
 
                      (label_ref (match_operand        3 "" ""))
 
                      (pc)))
 
   ]
 
  ""
 
  "#"
 
  ""
 
  [(set (pc)
 
        (if_then_else (eq (and:SI (match_dup  0)
 
                                  (match_dup 4))
 
                          (const_int 0))
 
                      (label_ref (match_dup 3))
 
                      (pc)))
 
   ]
 
  "operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));"
 
)
 
 
 
(define_insn_and_split "*tstbranchsi4m_ne"
 
  [(set (pc)
 
        (if_then_else (ne (zero_extract:SI (match_operand:SI  0 "register_operand"  "r")
 
                                           (match_operand  1 "rx_constshift_operand" "i")
 
                                           (match_operand  2 "rx_constshift_operand" "i"))
 
                          (const_int 0))
 
                      (label_ref (match_operand        3 "" ""))
 
                      (pc)))
 
   ]
 
  ""
 
  "#"
 
  ""
 
  [(set (pc)
 
        (if_then_else (ne (and:SI (match_dup  0)
 
                                  (match_dup 4))
 
                          (const_int 0))
 
                      (label_ref (match_dup 3))
 
                      (pc)))
 
   ]
 
  "operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));"
 
)
 
 
 
;; -----------------------------------------------------------------------------
 
 
(define_expand "cbranchsf4"
(define_expand "cbranchsf4"
  [(set (pc)
  [(set (pc)
        (if_then_else (match_operator:SF 0 "comparison_operator"
        (if_then_else (match_operator 0 "comparison_operator"
                                         [(match_operand:SF 1 "register_operand")
                                         [(match_operand:SF 1 "register_operand")
                                          (match_operand:SF 2 "rx_source_operand")])
                                          (match_operand:SF 2 "rx_source_operand")])
                      (label_ref (match_operand 3 ""))
                      (label_ref (match_operand 3 ""))
                      (pc)))
                      (pc)))
   ]
   ]
Line 201... Line 299...
  ""
  ""
)
)
 
 
(define_insn_and_split "*cbranchsf4_"
(define_insn_and_split "*cbranchsf4_"
  [(set (pc)
  [(set (pc)
        (if_then_else (most_cond:SF (match_operand:SF  0 "register_operand"  "r")
        (if_then_else (most_cond (match_operand:SF  0 "register_operand"  "r")
                                    (match_operand:SF  1 "rx_source_operand" "rFiQ"))
                                    (match_operand:SF  1 "rx_source_operand" "rFiQ"))
                      (label_ref (match_operand        2 "" ""))
                      (label_ref (match_operand        2 "" ""))
                      (pc)))
                      (pc)))
   ]
   ]
  "ALLOW_RX_FPU_INSNS"
  "ALLOW_RX_FPU_INSNS"

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