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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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Rev 280 |
Rev 378 |
Line 808... |
Line 808... |
&& last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
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&& last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
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{
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{
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rtx reg = SET_DEST (set);
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rtx reg = SET_DEST (set);
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rtx plus = SET_SRC (set);
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rtx plus = SET_SRC (set);
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rtx base = XEXP (plus, 1);
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rtx base = XEXP (plus, 1);
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rtx prev = prev_nonnote_insn (insn);
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rtx prev = prev_nonnote_nondebug_insn (insn);
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rtx prev_set = prev ? single_set (prev) : NULL_RTX;
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rtx prev_set = prev ? single_set (prev) : NULL_RTX;
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unsigned int regno = REGNO (reg);
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unsigned int regno = REGNO (reg);
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rtx index_reg = NULL_RTX;
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rtx index_reg = NULL_RTX;
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rtx reg_sum = NULL_RTX;
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rtx reg_sum = NULL_RTX;
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Line 1321... |
Line 1321... |
&& reg_set_luid[regno] == reg_set_luid[REGNO (src)]
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&& reg_set_luid[regno] == reg_set_luid[REGNO (src)]
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&& reg_base_reg[regno] == reg_base_reg[REGNO (src)]
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&& reg_base_reg[regno] == reg_base_reg[REGNO (src)]
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&& MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
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&& MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
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reg_mode[REGNO (src)]))
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reg_mode[REGNO (src)]))
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{
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{
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rtx next = next_nonnote_insn (insn);
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rtx next = next_nonnote_nondebug_insn (insn);
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rtx set = NULL_RTX;
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rtx set = NULL_RTX;
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if (next)
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if (next)
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set = single_set (next);
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set = single_set (next);
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if (set
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if (set
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&& SET_DEST (set) == reg
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&& SET_DEST (set) == reg
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