OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [gdb/] [or1k-tdep.c] - Diff between revs 178 and 225

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 178 Rev 225
Line 495... Line 495...
 
 
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/*!Determine if we are executing a delay slot
/*!Determine if we are executing a delay slot
 
 
   Looks at the instruction at the previous instruction to see if it was one
   Looks at the instruction at the previous instruction to see if it was one
   with a delay slot.
   with a delay slot. But it also has to be the address prior to NPC, because
 
   we may have just taken an exception.
 
 
   @param[in] gdbarch     The GDB architecture being used
   @param[in] gdbarch     The GDB architecture being used
   @param[in] this_frame  Information about THIS frame
   @param[in] this_frame  Information about THIS frame
 
 
   @return  1 (true) if this instruction is executing a delay slot, 0 (false)
   @return  1 (true) if this instruction is executing a delay slot, 0 (false)
Line 511... Line 512...
                                struct frame_info *this_frame )
                                struct frame_info *this_frame )
{
{
  struct regcache   *regcache = get_current_regcache ();
  struct regcache   *regcache = get_current_regcache ();
  ULONGEST           val;
  ULONGEST           val;
  CORE_ADDR          ppc;
  CORE_ADDR          ppc;
 
  CORE_ADDR          npc;
  int                index;
  int                index;
 
 
  /* Get and decode the previous instruction. */
  /* Get and the previous and current instruction addresses. If they are not
 
     adjacent, we cannot be in a delay slot. */
  regcache_cooked_read_unsigned (regcache, OR1K_PPC_REGNUM, &val);
  regcache_cooked_read_unsigned (regcache, OR1K_PPC_REGNUM, &val);
  ppc        = (CORE_ADDR)val;
  ppc        = (CORE_ADDR)val;
  index      = insn_decode (or1k_fetch_instruction (this_frame, ppc));
  regcache_cooked_read_unsigned (regcache, OR1K_NPC_REGNUM, &val);
 
  npc        = (CORE_ADDR) val;
 
 
 
  if (0x4 != (npc - ppc))
 
    {
 
      return  0;
 
    }
 
 
  /* We are only executing a delay slot if the previous instruction was a
  /* Decode the previous instruction to see if it was a branch or a jump, and
     branch or jump. */
     hence we are in a delay slot. */
 
  index = insn_decode (or1k_fetch_instruction (this_frame, ppc));
  return or32_opcodes[index].flags & OR32_IF_DELAY;
  return or32_opcodes[index].flags & OR32_IF_DELAY;
 
 
}       /* or1k_single_step_through_delay() */
}       /* or1k_single_step_through_delay() */
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.