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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [include/] [opcode/] [i386.h] - Diff between revs 157 and 225

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/* opcode/i386.h -- Intel 80386 opcode macros
/* opcode/i386.h -- Intel 80386 opcode macros
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   Free Software Foundation, Inc.
   Free Software Foundation, Inc.
 
 
   This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
   This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
 
 
   This program is free software; you can redistribute it and/or modify
   This program is free software; you can redistribute it and/or modify
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   operations with two register operands, where the source register is
   operations with two register operands, where the source register is
   %st, and destination register is %st(i).
   %st, and destination register is %st(i).
 
 
   The affected opcode map is dceX, dcfX, deeX, defX.  */
   The affected opcode map is dceX, dcfX, deeX, defX.  */
 
 
 
#ifndef OPCODE_I386_H
 
#define OPCODE_I386_H
 
 
#ifndef SYSV386_COMPAT
#ifndef SYSV386_COMPAT
/* Set non-zero for broken, compatible instructions.  Set to zero for
/* Set non-zero for broken, compatible instructions.  Set to zero for
   non-broken opcodes at your peril.  gcc generates SystemV/386
   non-broken opcodes at your peril.  gcc generates SystemV/386
   compatible instructions.  */
   compatible instructions.  */
#define SYSV386_COMPAT 1
#define SYSV386_COMPAT 1
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#define INT_OPCODE  0xcd
#define INT_OPCODE  0xcd
#define INT3_OPCODE 0xcc
#define INT3_OPCODE 0xcc
/* The opcode for the fwait instruction, which disassembler treats as a
/* The opcode for the fwait instruction, which disassembler treats as a
   prefix when it can.  */
   prefix when it can.  */
#define FWAIT_OPCODE 0x9b
#define FWAIT_OPCODE 0x9b
 
 
 
/* Instruction prefixes.
 
   NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
 
   part of the opcode.  Other prefixes may still appear between them
 
   and the 0x0f part of the opcode.  */
#define ADDR_PREFIX_OPCODE 0x67
#define ADDR_PREFIX_OPCODE 0x67
#define DATA_PREFIX_OPCODE 0x66
#define DATA_PREFIX_OPCODE 0x66
#define LOCK_PREFIX_OPCODE 0xf0
#define LOCK_PREFIX_OPCODE 0xf0
#define CS_PREFIX_OPCODE 0x2e
#define CS_PREFIX_OPCODE 0x2e
#define DS_PREFIX_OPCODE 0x3e
#define DS_PREFIX_OPCODE 0x3e
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#define TWO_BYTE_OPCODE_ESCAPE 0x0f
#define TWO_BYTE_OPCODE_ESCAPE 0x0f
#define NOP_OPCODE (char) 0x90
#define NOP_OPCODE (char) 0x90
 
 
/* register numbers */
/* register numbers */
#define EBP_REG_NUM 5
#define EAX_REG_NUM 0
 
#define ECX_REG_NUM 1
 
#define EDX_REG_NUM 2
 
#define EBX_REG_NUM 3
#define ESP_REG_NUM 4
#define ESP_REG_NUM 4
 
#define EBP_REG_NUM 5
 
#define ESI_REG_NUM 6
 
#define EDI_REG_NUM 7
 
 
/* modrm_byte.regmem for twobyte escape */
/* modrm_byte.regmem for twobyte escape */
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
/* index_base_byte.index for no index register addressing */
/* index_base_byte.index for no index register addressing */
#define NO_INDEX_REGISTER ESP_REG_NUM
#define NO_INDEX_REGISTER ESP_REG_NUM
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/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 
 
 
/* Extract fields from the mod/rm byte.  */
 
#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
 
#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
 
#define MODRM_RM_FIELD(modrm)  (((modrm) >> 0) & 7)
 
 
 
/* Extract fields from the sib byte.  */
 
#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
 
#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
 
#define SIB_BASE_FIELD(sib)  (((sib) >> 0) & 7)
 
 
/* x86-64 extension prefix.  */
/* x86-64 extension prefix.  */
#define REX_OPCODE      0x40
#define REX_OPCODE      0x40
 
 
 
/* Non-zero if OPCODE is the rex prefix.  */
 
#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
 
 
/* Indicates 64 bit operand size.  */
/* Indicates 64 bit operand size.  */
#define REX_W   8
#define REX_W   8
/* High extension to reg field of modrm byte.  */
/* High extension to reg field of modrm byte.  */
#define REX_R   4
#define REX_R   4
/* High extension to SIB index field.  */
/* High extension to SIB index field.  */
#define REX_X   2
#define REX_X   2
/* High extension to base field of modrm or SIB, or reg field of opcode.  */
/* High extension to base field of modrm or SIB, or reg field of opcode.  */
#define REX_B   1
#define REX_B   1
 
 
/* max operands per insn */
/* max operands per insn */
#define MAX_OPERANDS 4
#define MAX_OPERANDS 5
 
 
/* max immediates per insn (lcall, ljmp, insertq, extrq) */
/* max immediates per insn (lcall, ljmp, insertq, extrq) */
#define MAX_IMMEDIATE_OPERANDS 2
#define MAX_IMMEDIATE_OPERANDS 2
 
 
/* max memory refs per insn (string ops) */
/* max memory refs per insn (string ops) */
#define MAX_MEMORY_OPERANDS 2
#define MAX_MEMORY_OPERANDS 2
 
 
/* max size of insn mnemonics.  */
/* max size of insn mnemonics.  */
#define MAX_MNEM_SIZE 16
#define MAX_MNEM_SIZE 20
 
 
/* max size of register name in insn mnemonics.  */
/* max size of register name in insn mnemonics.  */
#define MAX_REG_NAME_SIZE 8
#define MAX_REG_NAME_SIZE 8
 
 
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#endif /* OPCODE_I386_H */
 
 
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