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/* mips.h. Mips opcode list for GDB, the GNU debugger.
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/* mips.h. Mips opcode list for GDB, the GNU debugger.
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Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
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Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
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2003, 2004, 2005, 2008
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2003, 2004, 2005, 2008, 2009
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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Contributed by Ralph Campbell and OSF
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Contributed by Ralph Campbell and OSF
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Commented and modified by Ian Lance Taylor, Cygnus Support
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Commented and modified by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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This file is part of GDB, GAS, and the GNU binutils.
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Line 213... |
#define OP_SH_UDI3 6
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#define OP_SH_UDI3 6
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#define OP_MASK_UDI3 0x7fff
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#define OP_MASK_UDI3 0x7fff
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#define OP_SH_UDI4 6
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#define OP_SH_UDI4 6
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#define OP_MASK_UDI4 0xfffff
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#define OP_MASK_UDI4 0xfffff
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/* Octeon */
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#define OP_SH_BBITIND 16
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#define OP_MASK_BBITIND 0x1f
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#define OP_SH_CINSPOS 6
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#define OP_MASK_CINSPOS 0x1f
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#define OP_SH_CINSLM1 11
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#define OP_MASK_CINSLM1 0x1f
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#define OP_SH_SEQI 6
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#define OP_MASK_SEQI 0x3ff
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/* This structure holds information for a particular instruction. */
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/* This structure holds information for a particular instruction. */
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struct mips_opcode
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struct mips_opcode
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{
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{
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/* The name of the instruction. */
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/* The name of the instruction. */
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Line 260... |
string are ignored when assembling, and written into the output
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string are ignored when assembling, and written into the output
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when disassembling.
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when disassembling.
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Each of these characters corresponds to a mask field defined above.
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Each of these characters corresponds to a mask field defined above.
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"1" 5 bit sync type (OP_*_SHAMT)
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"<" 5 bit shift amount (OP_*_SHAMT)
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"<" 5 bit shift amount (OP_*_SHAMT)
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">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
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">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
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"a" 26 bit target address (OP_*_TARGET)
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"a" 26 bit target address (OP_*_TARGET)
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"b" 5 bit base register (OP_*_RS)
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"b" 5 bit base register (OP_*_RS)
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"c" 10 bit breakpoint code (OP_*_CODE)
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"c" 10 bit breakpoint code (OP_*_CODE)
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Line 379... |
"+1" UDI immediate bits 6-10
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"+1" UDI immediate bits 6-10
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"+2" UDI immediate bits 6-15
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"+2" UDI immediate bits 6-15
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"+3" UDI immediate bits 6-20
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"+3" UDI immediate bits 6-20
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"+4" UDI immediate bits 6-25
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"+4" UDI immediate bits 6-25
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Octeon:
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"+x" Bit index field of bbit. Enforces: 0 <= index < 32.
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"+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
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otherwise skips to next candidate.
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"+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
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"+P" Position field of cins/exts aliasing cins32/exts32. Matches if
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32 <= pos < 64, otherwise skips to next candidate.
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"+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
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"+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32.
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"+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
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cint32/exts32. Enforces non-negative value and that
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pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
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position field is "+p" or "+P".
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Other:
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Other:
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"()" parens surrounding optional value
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"()" parens surrounding optional value
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"," separates operands
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"," separates operands
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"[]" brackets around index for vector-op scalar operand specifier (vr5400)
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"[]" brackets around index for vector-op scalar operand specifier (vr5400)
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"+" Start of extension sequence.
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"+" Start of extension sequence.
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Characters used so far, for quick reference when adding more:
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Characters used so far, for quick reference when adding more:
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"234567890"
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"1234567890"
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"%[]<>(),+:'@!$*&"
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"%[]<>(),+:'@!$*&"
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"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
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"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
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"abcdefghijklopqrstuvwxz"
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"abcdefghijklopqrstuvwxz"
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Extension character sequences used so far ("+" followed by the
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Extension character sequences used so far ("+" followed by the
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following), for quick reference when adding more:
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following), for quick reference when adding more:
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"1234"
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"1234"
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"ABCDEFGHIT"
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"ABCDEFGHIPQSTX"
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"t"
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"pstx"
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*/
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*/
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/* These are the bits which may be set in the pinfo field of an
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/* These are the bits which may be set in the pinfo field of an
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instructions, if it is not equal to INSN_MACRO. */
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instructions, if it is not equal to INSN_MACRO. */
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Line 479... |
#define FP_D 0x20000000
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#define FP_D 0x20000000
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/* Instruction is part of the tx39's integer multiply family. */
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/* Instruction is part of the tx39's integer multiply family. */
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#define INSN_MULT 0x40000000
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#define INSN_MULT 0x40000000
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/* Instruction synchronize shared memory. */
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/* Instruction synchronize shared memory. */
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#define INSN_SYNC 0x80000000
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#define INSN_SYNC 0x80000000
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/* Instruction is actually a macro. It should be ignored by the
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disassembler, and requires special treatment by the assembler. */
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#define INSN_MACRO 0xffffffff
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/* These are the bits which may be set in the pinfo2 field of an
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/* These are the bits which may be set in the pinfo2 field of an
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instruction. */
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instruction. */
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/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
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/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
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#define INSN2_ALIAS 0x00000001
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#define INSN2_ALIAS 0x00000001
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/* Instruction reads MDMX accumulator. */
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/* Instruction reads MDMX accumulator. */
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#define INSN2_READ_MDMX_ACC 0x00000002
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#define INSN2_READ_MDMX_ACC 0x00000002
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/* Instruction writes MDMX accumulator. */
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/* Instruction writes MDMX accumulator. */
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#define INSN2_WRITE_MDMX_ACC 0x00000004
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#define INSN2_WRITE_MDMX_ACC 0x00000004
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/* Macro uses single-precision floating-point instructions. This should
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/* Instruction is actually a macro. It should be ignored by the
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only be set for macros. For instructions, FP_S in pinfo carries the
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disassembler, and requires special treatment by the assembler. */
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same information. */
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#define INSN_MACRO 0xffffffff
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#define INSN2_M_FP_S 0x00000008
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/* Macro uses double-precision floating-point instructions. This should
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only be set for macros. For instructions, FP_D in pinfo carries the
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same information. */
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#define INSN2_M_FP_D 0x00000010
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/* Masks used to mark instructions to indicate which MIPS ISA level
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/* Masks used to mark instructions to indicate which MIPS ISA level
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they were introduced in. INSN_ISA_MASK masks an enumeration that
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they were introduced in. INSN_ISA_MASK masks an enumeration that
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specifies the base ISA level(s). The remainder of a 32-bit
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specifies the base ISA level(s). The remainder of a 32-bit
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word constructed using these macros is a bitmask of the remaining
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word constructed using these macros is a bitmask of the remaining
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Line 541... |
is non-zero. */
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is non-zero. */
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static const unsigned int mips_isa_table[] =
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static const unsigned int mips_isa_table[] =
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{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
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{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
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/* Masks used for Chip specific instructions. */
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/* Masks used for Chip specific instructions. */
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#define INSN_CHIP_MASK 0xc3ff0800
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#define INSN_CHIP_MASK 0xc3ff0820
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/* Cavium Networks Octeon instructions. */
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/* Cavium Networks Octeon instructions. */
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#define INSN_OCTEON 0x00000800
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#define INSN_OCTEON 0x00000800
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/* Masks used for MIPS-defined ASEs. */
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/* Masks used for MIPS-defined ASEs. */
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Line 590... |
#define INSN_DSPR2 0x20000000
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#define INSN_DSPR2 0x20000000
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/* ST Microelectronics Loongson 2E. */
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/* ST Microelectronics Loongson 2E. */
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#define INSN_LOONGSON_2E 0x40000000
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#define INSN_LOONGSON_2E 0x40000000
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/* ST Microelectronics Loongson 2F. */
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/* ST Microelectronics Loongson 2F. */
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#define INSN_LOONGSON_2F 0x80000000
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#define INSN_LOONGSON_2F 0x80000000
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/* RMI Xlr instruction */
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#define INSN_XLR 0x00000020
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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#define ISA_UNKNOWN 0 /* Gas internal use. */
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#define ISA_UNKNOWN 0 /* Gas internal use. */
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#define ISA_MIPS1 INSN_ISA1
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#define ISA_MIPS1 INSN_ISA1
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Line 632... |
#define CPU_RM7000 7000
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#define CPU_RM7000 7000
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#define CPU_R8000 8000
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#define CPU_R8000 8000
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#define CPU_RM9000 9000
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#define CPU_RM9000 9000
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#define CPU_R10000 10000
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#define CPU_R10000 10000
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#define CPU_R12000 12000
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#define CPU_R12000 12000
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#define CPU_R14000 14000
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#define CPU_R16000 16000
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#define CPU_MIPS16 16
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#define CPU_MIPS16 16
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#define CPU_MIPS32 32
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#define CPU_MIPS32 32
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#define CPU_MIPS32R2 33
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#define CPU_MIPS32R2 33
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#define CPU_MIPS5 5
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#define CPU_MIPS5 5
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#define CPU_MIPS64 64
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#define CPU_MIPS64 64
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#define CPU_MIPS64R2 65
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#define CPU_MIPS64R2 65
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#define CPU_SB1 12310201 /* octal 'SB', 01. */
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#define CPU_SB1 12310201 /* octal 'SB', 01. */
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#define CPU_LOONGSON_2E 3001
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#define CPU_LOONGSON_2E 3001
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#define CPU_LOONGSON_2F 3002
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#define CPU_LOONGSON_2F 3002
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#define CPU_OCTEON 6501
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#define CPU_OCTEON 6501
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#define CPU_XLR 887682 /* decimal 'XLR' */
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/* Test for membership in an ISA including chip specific ISAs. INSN
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/* Test for membership in an ISA including chip specific ISAs. INSN
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is pointer to an element of the opcode table; ISA is the specified
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is pointer to an element of the opcode table; ISA is the specified
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ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
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ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
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test, or zero if no CPU specific ISA test is desired. */
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test, or zero if no CPU specific ISA test is desired. */
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| Line 627... |
Line 664... |
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
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|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
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|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
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|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
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|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
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|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
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|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
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|| ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
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|| cpu == CPU_R16000) \
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&& ((insn)->membership & INSN_10000) != 0) \
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&& ((insn)->membership & INSN_10000) != 0) \
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|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
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|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
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|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
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|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
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|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
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|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
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|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
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|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
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| Line 640... |
Line 678... |
&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
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&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
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|| (cpu == CPU_LOONGSON_2F \
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|| (cpu == CPU_LOONGSON_2F \
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&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
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&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
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|| (cpu == CPU_OCTEON \
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|| (cpu == CPU_OCTEON \
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&& ((insn)->membership & INSN_OCTEON) != 0) \
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&& ((insn)->membership & INSN_OCTEON) != 0) \
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|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
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|| 0) /* Please keep this term for easier source merging. */
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|| 0) /* Please keep this term for easier source merging. */
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/* This is a list of macro expanded instructions.
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/* This is a list of macro expanded instructions.
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_I appended means immediate
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_I appended means immediate
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| Line 772... |
Line 811... |
M_LWL_A,
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M_LWL_A,
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M_LWL_AB,
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M_LWL_AB,
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M_LWR_A,
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M_LWR_A,
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M_LWR_AB,
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M_LWR_AB,
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M_LWU_AB,
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M_LWU_AB,
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M_MSGSND,
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M_MSGLD,
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M_MSGLD_T,
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M_MSGWAIT,
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M_MSGWAIT_T,
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M_MOVE,
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M_MOVE,
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M_MUL,
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M_MUL,
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M_MUL_I,
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M_MUL_I,
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M_MULO,
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M_MULO,
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M_MULO_I,
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M_MULO_I,
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| Line 953... |
Line 997... |
#define MIPS16OP_MASK_MOVE32Z 0x7
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#define MIPS16OP_MASK_MOVE32Z 0x7
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#define MIPS16OP_SH_MOVE32Z 0
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#define MIPS16OP_SH_MOVE32Z 0
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#define MIPS16OP_MASK_IMM6 0x3f
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#define MIPS16OP_MASK_IMM6 0x3f
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#define MIPS16OP_SH_IMM6 5
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#define MIPS16OP_SH_IMM6 5
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/* These are the characters which may appears in the args field of an
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/* These are the characters which may appears in the args field of a MIPS16
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instruction. They appear in the order in which the fields appear
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instruction. They appear in the order in which the fields appear when the
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when the instruction is used. Commas and parentheses in the args
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instruction is used. Commas and parentheses in the args string are ignored
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string are ignored when assembling, and written into the output
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when assembling, and written into the output when disassembling.
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when disassembling.
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"y" 3 bit register (MIPS16OP_*_RY)
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"y" 3 bit register (MIPS16OP_*_RY)
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"x" 3 bit register (MIPS16OP_*_RX)
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"x" 3 bit register (MIPS16OP_*_RX)
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"z" 3 bit register (MIPS16OP_*_RZ)
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"z" 3 bit register (MIPS16OP_*_RZ)
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"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
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"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
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