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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [include/] [opcode/] [mips.h] - Diff between revs 157 and 225

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/* mips.h.  Mips opcode list for GDB, the GNU debugger.
/* mips.h.  Mips opcode list for GDB, the GNU debugger.
   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   2003, 2004, 2005, 2008
   2003, 2004, 2005, 2008, 2009
   Free Software Foundation, Inc.
   Free Software Foundation, Inc.
   Contributed by Ralph Campbell and OSF
   Contributed by Ralph Campbell and OSF
   Commented and modified by Ian Lance Taylor, Cygnus Support
   Commented and modified by Ian Lance Taylor, Cygnus Support
 
 
This file is part of GDB, GAS, and the GNU binutils.
This file is part of GDB, GAS, and the GNU binutils.
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#define OP_SH_UDI3              6
#define OP_SH_UDI3              6
#define OP_MASK_UDI3            0x7fff
#define OP_MASK_UDI3            0x7fff
#define OP_SH_UDI4              6
#define OP_SH_UDI4              6
#define OP_MASK_UDI4            0xfffff
#define OP_MASK_UDI4            0xfffff
 
 
 
/* Octeon */
 
#define OP_SH_BBITIND           16
 
#define OP_MASK_BBITIND         0x1f
 
#define OP_SH_CINSPOS           6
 
#define OP_MASK_CINSPOS         0x1f
 
#define OP_SH_CINSLM1           11
 
#define OP_MASK_CINSLM1         0x1f
 
#define OP_SH_SEQI              6
 
#define OP_MASK_SEQI            0x3ff
 
 
/* This structure holds information for a particular instruction.  */
/* This structure holds information for a particular instruction.  */
 
 
struct mips_opcode
struct mips_opcode
{
{
  /* The name of the instruction.  */
  /* The name of the instruction.  */
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   string are ignored when assembling, and written into the output
   string are ignored when assembling, and written into the output
   when disassembling.
   when disassembling.
 
 
   Each of these characters corresponds to a mask field defined above.
   Each of these characters corresponds to a mask field defined above.
 
 
 
   "1" 5 bit sync type (OP_*_SHAMT)
   "<" 5 bit shift amount (OP_*_SHAMT)
   "<" 5 bit shift amount (OP_*_SHAMT)
   ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
   ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
   "a" 26 bit target address (OP_*_TARGET)
   "a" 26 bit target address (OP_*_TARGET)
   "b" 5 bit base register (OP_*_RS)
   "b" 5 bit base register (OP_*_RS)
   "c" 10 bit breakpoint code (OP_*_CODE)
   "c" 10 bit breakpoint code (OP_*_CODE)
Line 368... Line 379...
   "+1" UDI immediate bits 6-10
   "+1" UDI immediate bits 6-10
   "+2" UDI immediate bits 6-15
   "+2" UDI immediate bits 6-15
   "+3" UDI immediate bits 6-20
   "+3" UDI immediate bits 6-20
   "+4" UDI immediate bits 6-25
   "+4" UDI immediate bits 6-25
 
 
 
   Octeon:
 
   "+x" Bit index field of bbit.  Enforces: 0 <= index < 32.
 
   "+X" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,
 
        otherwise skips to next candidate.
 
   "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
 
   "+P" Position field of cins/exts aliasing cins32/exts32.  Matches if
 
        32 <= pos < 64, otherwise skips to next candidate.
 
   "+Q" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.
 
   "+s" Length-minus-one field of cins/exts.  Enforces: 0 <= lenm1 < 32.
 
   "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
 
        cint32/exts32.  Enforces non-negative value and that
 
        pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
 
        position field is "+p" or "+P".
 
 
   Other:
   Other:
   "()" parens surrounding optional value
   "()" parens surrounding optional value
   ","  separates operands
   ","  separates operands
   "[]" brackets around index for vector-op scalar operand specifier (vr5400)
   "[]" brackets around index for vector-op scalar operand specifier (vr5400)
   "+"  Start of extension sequence.
   "+"  Start of extension sequence.
 
 
   Characters used so far, for quick reference when adding more:
   Characters used so far, for quick reference when adding more:
   "234567890"
   "1234567890"
   "%[]<>(),+:'@!$*&"
   "%[]<>(),+:'@!$*&"
   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
   "abcdefghijklopqrstuvwxz"
   "abcdefghijklopqrstuvwxz"
 
 
   Extension character sequences used so far ("+" followed by the
   Extension character sequences used so far ("+" followed by the
   following), for quick reference when adding more:
   following), for quick reference when adding more:
   "1234"
   "1234"
   "ABCDEFGHIT"
   "ABCDEFGHIPQSTX"
   "t"
   "pstx"
*/
*/
 
 
/* These are the bits which may be set in the pinfo field of an
/* These are the bits which may be set in the pinfo field of an
   instructions, if it is not equal to INSN_MACRO.  */
   instructions, if it is not equal to INSN_MACRO.  */
 
 
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#define FP_D                        0x20000000
#define FP_D                        0x20000000
/* Instruction is part of the tx39's integer multiply family.    */
/* Instruction is part of the tx39's integer multiply family.    */
#define INSN_MULT                   0x40000000
#define INSN_MULT                   0x40000000
/* Instruction synchronize shared memory.  */
/* Instruction synchronize shared memory.  */
#define INSN_SYNC                   0x80000000
#define INSN_SYNC                   0x80000000
 
/* Instruction is actually a macro.  It should be ignored by the
 
   disassembler, and requires special treatment by the assembler.  */
 
#define INSN_MACRO                  0xffffffff
 
 
/* These are the bits which may be set in the pinfo2 field of an
/* These are the bits which may be set in the pinfo2 field of an
   instruction. */
   instruction. */
 
 
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
#define INSN2_ALIAS                 0x00000001
#define INSN2_ALIAS                 0x00000001
/* Instruction reads MDMX accumulator. */
/* Instruction reads MDMX accumulator. */
#define INSN2_READ_MDMX_ACC         0x00000002
#define INSN2_READ_MDMX_ACC         0x00000002
/* Instruction writes MDMX accumulator. */
/* Instruction writes MDMX accumulator. */
#define INSN2_WRITE_MDMX_ACC        0x00000004
#define INSN2_WRITE_MDMX_ACC        0x00000004
 
/* Macro uses single-precision floating-point instructions.  This should
/* Instruction is actually a macro.  It should be ignored by the
   only be set for macros.  For instructions, FP_S in pinfo carries the
   disassembler, and requires special treatment by the assembler.  */
   same information.  */
#define INSN_MACRO                  0xffffffff
#define INSN2_M_FP_S                0x00000008
 
/* Macro uses double-precision floating-point instructions.  This should
 
   only be set for macros.  For instructions, FP_D in pinfo carries the
 
   same information.  */
 
#define INSN2_M_FP_D                0x00000010
 
 
/* Masks used to mark instructions to indicate which MIPS ISA level
/* Masks used to mark instructions to indicate which MIPS ISA level
   they were introduced in.  INSN_ISA_MASK masks an enumeration that
   they were introduced in.  INSN_ISA_MASK masks an enumeration that
   specifies the base ISA level(s).  The remainder of a 32-bit
   specifies the base ISA level(s).  The remainder of a 32-bit
   word constructed using these macros is a bitmask of the remaining
   word constructed using these macros is a bitmask of the remaining
Line 509... Line 541...
   is non-zero.  */
   is non-zero.  */
static const unsigned int mips_isa_table[] =
static const unsigned int mips_isa_table[] =
  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 
 
/* Masks used for Chip specific instructions.  */
/* Masks used for Chip specific instructions.  */
#define INSN_CHIP_MASK            0xc3ff0800
#define INSN_CHIP_MASK            0xc3ff0820
 
 
/* Cavium Networks Octeon instructions.  */
/* Cavium Networks Octeon instructions.  */
#define INSN_OCTEON               0x00000800
#define INSN_OCTEON               0x00000800
 
 
/* Masks used for MIPS-defined ASEs.  */
/* Masks used for MIPS-defined ASEs.  */
Line 558... Line 590...
#define INSN_DSPR2                0x20000000
#define INSN_DSPR2                0x20000000
/* ST Microelectronics Loongson 2E.  */
/* ST Microelectronics Loongson 2E.  */
#define INSN_LOONGSON_2E          0x40000000
#define INSN_LOONGSON_2E          0x40000000
/* ST Microelectronics Loongson 2F.  */
/* ST Microelectronics Loongson 2F.  */
#define INSN_LOONGSON_2F          0x80000000
#define INSN_LOONGSON_2F          0x80000000
 
/* RMI Xlr instruction */
 
#define INSN_XLR                  0x00000020
 
 
/* MIPS ISA defines, use instead of hardcoding ISA level.  */
/* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
 
#define       ISA_UNKNOWN     0               /* Gas internal use.  */
#define       ISA_UNKNOWN     0               /* Gas internal use.  */
#define       ISA_MIPS1       INSN_ISA1
#define       ISA_MIPS1       INSN_ISA1
Line 598... Line 632...
#define CPU_RM7000      7000
#define CPU_RM7000      7000
#define CPU_R8000       8000
#define CPU_R8000       8000
#define CPU_RM9000      9000
#define CPU_RM9000      9000
#define CPU_R10000      10000
#define CPU_R10000      10000
#define CPU_R12000      12000
#define CPU_R12000      12000
 
#define CPU_R14000      14000
 
#define CPU_R16000      16000
#define CPU_MIPS16      16
#define CPU_MIPS16      16
#define CPU_MIPS32      32
#define CPU_MIPS32      32
#define CPU_MIPS32R2    33
#define CPU_MIPS32R2    33
#define CPU_MIPS5       5
#define CPU_MIPS5       5
#define CPU_MIPS64      64
#define CPU_MIPS64      64
#define CPU_MIPS64R2    65
#define CPU_MIPS64R2    65
#define CPU_SB1         12310201        /* octal 'SB', 01.  */
#define CPU_SB1         12310201        /* octal 'SB', 01.  */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
#define CPU_LOONGSON_2F 3002
#define CPU_OCTEON      6501
#define CPU_OCTEON      6501
 
#define CPU_XLR         887682          /* decimal 'XLR'   */
 
 
/* Test for membership in an ISA including chip specific ISAs.  INSN
/* Test for membership in an ISA including chip specific ISAs.  INSN
   is pointer to an element of the opcode table; ISA is the specified
   is pointer to an element of the opcode table; ISA is the specified
   ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
   ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
   test, or zero if no CPU specific ISA test is desired.  */
   test, or zero if no CPU specific ISA test is desired.  */
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     || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)     \
     || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)     \
     || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)     \
     || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)     \
     || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)      \
     || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)      \
     || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)     \
     || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)     \
     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)      \
     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)      \
     || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
     || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000   \
 
          || cpu == CPU_R16000)                                         \
         && ((insn)->membership & INSN_10000) != 0)                      \
         && ((insn)->membership & INSN_10000) != 0)                      \
     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
     || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)      \
     || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)      \
     || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)     \
     || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)     \
     || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)     \
     || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)     \
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         && ((insn)->membership & INSN_LOONGSON_2E) != 0)               \
         && ((insn)->membership & INSN_LOONGSON_2E) != 0)               \
     || (cpu == CPU_LOONGSON_2F                                         \
     || (cpu == CPU_LOONGSON_2F                                         \
         && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
         && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
     || (cpu == CPU_OCTEON                                              \
     || (cpu == CPU_OCTEON                                              \
         && ((insn)->membership & INSN_OCTEON) != 0)                     \
         && ((insn)->membership & INSN_OCTEON) != 0)                     \
 
     || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \
     || 0)       /* Please keep this term for easier source merging.  */
     || 0)       /* Please keep this term for easier source merging.  */
 
 
/* This is a list of macro expanded instructions.
/* This is a list of macro expanded instructions.
 
 
   _I appended means immediate
   _I appended means immediate
Line 772... Line 811...
  M_LWL_A,
  M_LWL_A,
  M_LWL_AB,
  M_LWL_AB,
  M_LWR_A,
  M_LWR_A,
  M_LWR_AB,
  M_LWR_AB,
  M_LWU_AB,
  M_LWU_AB,
 
  M_MSGSND,
 
  M_MSGLD,
 
  M_MSGLD_T,
 
  M_MSGWAIT,
 
  M_MSGWAIT_T,
  M_MOVE,
  M_MOVE,
  M_MUL,
  M_MUL,
  M_MUL_I,
  M_MUL_I,
  M_MULO,
  M_MULO,
  M_MULO_I,
  M_MULO_I,
Line 953... Line 997...
#define MIPS16OP_MASK_MOVE32Z   0x7
#define MIPS16OP_MASK_MOVE32Z   0x7
#define MIPS16OP_SH_MOVE32Z     0
#define MIPS16OP_SH_MOVE32Z     0
#define MIPS16OP_MASK_IMM6      0x3f
#define MIPS16OP_MASK_IMM6      0x3f
#define MIPS16OP_SH_IMM6        5
#define MIPS16OP_SH_IMM6        5
 
 
/* These are the characters which may appears in the args field of an
/* These are the characters which may appears in the args field of a MIPS16
   instruction.  They appear in the order in which the fields appear
   instruction.  They appear in the order in which the fields appear when the
   when the instruction is used.  Commas and parentheses in the args
   instruction is used.  Commas and parentheses in the args string are ignored
   string are ignored when assembling, and written into the output
   when assembling, and written into the output when disassembling.
   when disassembling.
 
 
 
   "y" 3 bit register (MIPS16OP_*_RY)
   "y" 3 bit register (MIPS16OP_*_RY)
   "x" 3 bit register (MIPS16OP_*_RX)
   "x" 3 bit register (MIPS16OP_*_RX)
   "z" 3 bit register (MIPS16OP_*_RZ)
   "z" 3 bit register (MIPS16OP_*_RZ)
   "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
   "Z" 3 bit register (MIPS16OP_*_MOVE32Z)

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