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/* ppc.h -- Header file for PowerPC opcode table
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/* ppc.h -- Header file for PowerPC opcode table
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Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
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Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
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2007 Free Software Foundation, Inc.
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2007, 2008, 2009 Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef PPC_H
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#ifndef PPC_H
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#define PPC_H
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#define PPC_H
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#include "bfd_stdint.h"
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typedef uint64_t ppc_cpu_t;
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/* The opcode table is an array of struct powerpc_opcode. */
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/* The opcode table is an array of struct powerpc_opcode. */
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struct powerpc_opcode
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struct powerpc_opcode
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{
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{
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/* The opcode name. */
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/* The opcode name. */
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unsigned long mask;
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unsigned long mask;
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/* One bit flags for the opcode. These are used to indicate which
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/* One bit flags for the opcode. These are used to indicate which
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specific processors support the instructions. The defined values
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specific processors support the instructions. The defined values
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are listed below. */
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are listed below. */
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unsigned long flags;
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ppc_cpu_t flags;
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/* One bit flags for the opcode. These are used to indicate which
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specific processors no longer support the instructions. The defined
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values are listed below. */
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ppc_cpu_t deprecated;
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/* An array of operand codes. Each code is an index into the
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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appear in assembly code, and are terminated by a zero. */
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unsigned char operands[8];
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unsigned char operands[8];
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#define PPC_OPCODE_440 0x2000
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#define PPC_OPCODE_440 0x2000
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/* Opcode is only supported by Power4 architecture. */
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/* Opcode is only supported by Power4 architecture. */
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#define PPC_OPCODE_POWER4 0x4000
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#define PPC_OPCODE_POWER4 0x4000
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/* Opcode isn't supported by Power4 architecture. */
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/* Opcode is only supported by Power7 architecture. */
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#define PPC_OPCODE_NOPOWER4 0x8000
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#define PPC_OPCODE_POWER7 0x8000
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/* Opcode is only supported by POWERPC Classic architecture. */
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/* Opcode is only supported by POWERPC Classic architecture. */
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#define PPC_OPCODE_CLASSIC 0x10000
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#define PPC_OPCODE_CLASSIC 0x10000
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/* Opcode is only supported by e500x2 Core. */
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/* Opcode is only supported by e500x2 Core. */
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#define PPC_OPCODE_CELL 0x8000000
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#define PPC_OPCODE_CELL 0x8000000
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/* Opcode is supported by CPUs with paired singles support. */
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/* Opcode is supported by CPUs with paired singles support. */
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#define PPC_OPCODE_PPCPS 0x10000000
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#define PPC_OPCODE_PPCPS 0x10000000
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/* Opcode is supported by Power E500MC */
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#define PPC_OPCODE_E500MC 0x20000000
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/* Opcode is supported by PowerPC 405 processor. */
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#define PPC_OPCODE_405 0x40000000
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/* Opcode is supported by Vector-Scalar (VSX) Unit */
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#define PPC_OPCODE_VSX 0x80000000
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/* Opcode is supported by A2. */
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#define PPC_OPCODE_A2 0x100000000ULL
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/* Opcode is supported by PowerPC 476 processor. */
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#define PPC_OPCODE_476 0x200000000ULL
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/* A macro to extract the major opcode from an instruction. */
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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/* The operands table is an array of struct powerpc_operand. */
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/* The operands table is an array of struct powerpc_operand. */
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the operand value is illegal, *ERRMSG will be set to a warning
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged (most operands
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operand value is legal, *ERRMSG will be unchanged (most operands
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can accept any value). */
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can accept any value). */
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unsigned long (*insert)
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unsigned long (*insert)
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(unsigned long instruction, long op, int dialect, const char **errmsg);
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(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
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/* Extraction function. This is used by the disassembler. To
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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If it is NULL, compute
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instruction value. It will return the value of the operand. If
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed. */
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operand is valid, *INVALID will not be changed. */
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long (*extract) (unsigned long instruction, int dialect, int *invalid);
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long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
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/* One bit syntax flags. */
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/* One bit syntax flags. */
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unsigned long flags;
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unsigned long flags;
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};
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};
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/* This operand is for the DQ field in a DQ form instruction. */
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/* This operand is for the DQ field in a DQ form instruction. */
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#define PPC_OPERAND_DQ (0x8000)
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#define PPC_OPERAND_DQ (0x8000)
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/* Valid range of operand is 0..n rather than 0..n-1. */
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/* Valid range of operand is 0..n rather than 0..n-1. */
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#define PPC_OPERAND_PLUS1 (0x10000)
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#define PPC_OPERAND_PLUS1 (0x10000)
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/* Xilinx APU and FSL related operands */
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#define PPC_OPERAND_FSL (0x20000)
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#define PPC_OPERAND_FCR (0x40000)
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#define PPC_OPERAND_UDI (0x80000)
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/* This operand names a vector-scalar unit register. The disassembler
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prints these with a leading 'vs'. */
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#define PPC_OPERAND_VSR (0x100000)
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/* The POWER and PowerPC assemblers use a few macros. We keep them
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/* The POWER and PowerPC assemblers use a few macros. We keep them
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with the operands table for simplicity. The macro table is an
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with the operands table for simplicity. The macro table is an
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array of struct powerpc_macro. */
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array of struct powerpc_macro. */
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unsigned int operands;
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unsigned int operands;
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/* One bit flags for the opcode. These are used to indicate which
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/* One bit flags for the opcode. These are used to indicate which
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specific processors support the instructions. The values are the
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specific processors support the instructions. The values are the
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same as those for the struct powerpc_opcode flags field. */
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same as those for the struct powerpc_opcode flags field. */
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unsigned long flags;
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ppc_cpu_t flags;
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/* A format string to turn the macro into a normal instruction.
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/* A format string to turn the macro into a normal instruction.
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Each %N in the string is replaced with operand number N (zero
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Each %N in the string is replaced with operand number N (zero
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based). */
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based). */
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const char *format;
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const char *format;
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};
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};
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extern const struct powerpc_macro powerpc_macros[];
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extern const struct powerpc_macro powerpc_macros[];
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extern const int powerpc_num_macros;
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extern const int powerpc_num_macros;
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extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
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#endif /* PPC_H */
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#endif /* PPC_H */
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No newline at end of file
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