OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [include/] [opcode/] [tic30.h] - Diff between revs 157 and 225

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 157 Rev 225
Line 1... Line 1...
/* tic30.h -- Header file for TI TMS320C30 opcode table
/* tic30.h -- Header file for TI TMS320C30 opcode table
   Copyright 1998 Free Software Foundation, Inc.
   Copyright 1998, 2005, 2009 Free Software Foundation, Inc.
   Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
   Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
 
 
This file is part of GDB, GAS, and the GNU binutils.
This file is part of GDB, GAS, and the GNU binutils.
 
 
GDB, GAS, and the GNU binutils are free software; you can redistribute
GDB, GAS, and the GNU binutils are free software; you can redistribute
Line 239... Line 239...
#define Imm_None  0
#define Imm_None  0
#define Imm_Float 1
#define Imm_Float 1
#define Imm_SInt  2
#define Imm_SInt  2
#define Imm_UInt  3
#define Imm_UInt  3
}
}
template;
insn_template;
 
 
static const template tic30_optab[] = {
static const insn_template tic30_optab[] = {
  { "absf"   ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
  { "absf"   ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
  { "absi"   ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
  { "absi"   ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
  { "addc"   ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
  { "addc"   ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
  { "addc3"  ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
  { "addc3"  ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
  { "addf"   ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
  { "addf"   ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
Line 602... Line 602...
  { "xor"    ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
  { "xor"    ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
  { "xor3"   ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
  { "xor3"   ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
  { ""       ,0,0x00000000,0,           { 0, 0, 0 }, 0 }
  { ""       ,0,0x00000000,0,           { 0, 0, 0 }, 0 }
};
};
 
 
static const template *const tic30_optab_end =
static const insn_template *const tic30_optab_end =
  tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
  tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
 
 
typedef struct {
typedef struct {
  char *name;
  char *name;
  unsigned int operands_1;
  unsigned int operands_1;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.