OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [opcodes/] [arm-dis.c] - Diff between revs 157 and 225

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 157 Rev 225
Line 1... Line 1...
/* Instruction printing code for the ARM
/* Instruction printing code for the ARM
   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
   2007, Free Software Foundation, Inc.
   2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation, Inc.
   Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   Modification by James G. Smith (jsmith@cygnus.co.uk)
   Modification by James G. Smith (jsmith@cygnus.co.uk)
 
 
   This file is part of libopcodes.
   This file is part of libopcodes.
 
 
Line 46... Line 46...
#endif
#endif
 
 
struct opcode32
struct opcode32
{
{
  unsigned long arch;           /* Architecture defining this insn.  */
  unsigned long arch;           /* Architecture defining this insn.  */
  unsigned long value, mask;    /* Recognise insn if (op&mask)==value.  */
  unsigned long value;          /* If arch == 0 then value is a sentinel.  */
 
  unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  const char *assembler;        /* How to disassemble this insn.  */
  const char *assembler;        /* How to disassemble this insn.  */
};
};
 
 
struct opcode16
struct opcode16
{
{
Line 101... Line 102...
   %Z                   print the Immediate of a WSHUFH instruction.
   %Z                   print the Immediate of a WSHUFH instruction.
   %l                   like 'A' except use byte offsets for 'B' & 'H'
   %l                   like 'A' except use byte offsets for 'B' & 'H'
                        versions.
                        versions.
   %i                   print 5-bit immediate in bits 8,3..0
   %i                   print 5-bit immediate in bits 8,3..0
                        (print "32" when 0)
                        (print "32" when 0)
   %r                   print register offset address for wldt/wstr instruction
   %r                   print register offset address for wldt/wstr instruction.  */
*/
 
 
enum
 
{
 
  SENTINEL_IWMMXT_START = 1,
 
  SENTINEL_IWMMXT_END,
 
  SENTINEL_GENERIC_START
 
} opcode_sentinels;
 
 
 
#define UNDEFINED_INSTRUCTION "undefined instruction %0-31x"
 
 
/* Common coprocessor opcodes shared between Arm and Thumb-2.  */
/* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 
 
static const struct opcode32 coprocessor_opcodes[] =
static const struct opcode32 coprocessor_opcodes[] =
{
{
Line 116... Line 125...
  {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
  {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
  {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
  {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
  {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
  {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 
 
  /* Intel Wireless MMX technology instructions.  */
  /* Intel Wireless MMX technology instructions.  */
#define FIRST_IWMMXT_INSN 0x0e130130
  { 0, SENTINEL_IWMMXT_START, 0, "" },
#define IWMMXT_INSN_COUNT 73
 
  {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
  {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
  {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
  {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
  {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
  {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
  {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
  {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
  {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
  {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
Line 132... Line 140...
  {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
  {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
  {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
  {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
  {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
  {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
  {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
  {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
  {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
  {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
  {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
Line 193... Line 201...
  {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
  {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
  {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 
  { 0, SENTINEL_IWMMXT_END, 0, "" },
 
 
  /* Floating point coprocessor (FPA) instructions */
  /* Floating point coprocessor (FPA) instructions.  */
  {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
Line 236... Line 245...
  {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
  {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
  {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
  {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
  {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
  {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
  {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A\t; (stc%22'l%c %8-11d, cr%12-15d, %A)"},
  {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
  {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A\t; (ldc%22'l%c %8-11d, cr%12-15d, %A)"},
 
 
  /* Register load/store */
  /* Register load/store.  */
  {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"},
  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
  {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"},
  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
  {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
  {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
  {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
  {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 
  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
 
  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
 
  {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 
  {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 
 
 
  {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 
  {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 
  {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 
  {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 
 
  /* Data transfer between ARM and NEON registers */
  /* Data transfer between ARM and NEON registers.  */
  {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
  {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
  {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
  {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
  {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
  {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
  {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
  {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
  {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
  {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
Line 262... Line 286...
  {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
  {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
  {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
  {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
  {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
  {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
  {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
  {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
  {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
  {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 
  /* Half-precision conversion instructions.  */
  /* Floating point coprocessor (VFP) instructions */
  {FPU_NEON_FP16,   0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"},
  {FPU_NEON_FP16,   0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
 
  {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
  /* Floating point coprocessor (VFP) instructions.  */
  {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "fmxr%c\tmvfr1, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "fmxr%c\tmvfr0, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
  {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
  {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
  {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
  {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
  {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
  {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr1"},
  {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
  {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr0"},
  {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
  {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
  {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
  {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
  {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
  {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},
  {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
  {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
  {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"},
  {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
  {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
  {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"},
  {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"},
  {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
  {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"},
  {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
  {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"},
  {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
  {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"},
  {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
  {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"},
  {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
  {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
  {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"},
  {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"},
  {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
  {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
  {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"},
  {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"},
  {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
  {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
  {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"},
  {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
  {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
  {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"},
  {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
  {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"},
  {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
  {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"},
  {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"},
  {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
  {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"},
  {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
  {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"},
  {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
  {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"},
  {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
  {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
  {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
  {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"},
  {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
  {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"},
  {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
  {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"},
  {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
  {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
  {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
  {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
  {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"},
  {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
  {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"},
 
  {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"},
 
  {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"},
 
  {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"},
 
  {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"},
 
  {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"},
 
  {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"},
 
  {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"},
 
  {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"},
 
  {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"},
 
 
 
  /* Cirrus coprocessor instructions.  */
  /* Cirrus coprocessor instructions.  */
  {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
  {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
  {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
  {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
  {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
  {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
Line 434... Line 445...
  {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
  {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
  {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
  {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
  {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
  {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
  {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
  {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 
 
  /* Generic coprocessor instructions */
  /* Generic coprocessor instructions.  */
  {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
  { 0, SENTINEL_GENERIC_START, 0, "" },
  {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
  {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
 
  {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
  {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
  {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
  {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
  {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 
 
  /* V6 coprocessor instructions */
  /* V6 coprocessor instructions.  */
  {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
  {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
  {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
  {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
 
 
  /* V5 coprocessor instructions */
  /* V5 coprocessor instructions.  */
  {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
  {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
  {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
  {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
  {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
  {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
Line 485... Line 497...
   %<bitfield>Tn        print short scaled width limited by n
   %<bitfield>Tn        print short scaled width limited by n
   %<bitfield>Un        print long scaled width limited by n
   %<bitfield>Un        print long scaled width limited by n
 
 
   %<bitfield>'c        print specified char iff bitfield is all ones
   %<bitfield>'c        print specified char iff bitfield is all ones
   %<bitfield>`c        print specified char iff bitfield is all zeroes
   %<bitfield>`c        print specified char iff bitfield is all zeroes
   %<bitfield>?ab...    select from array of values in big endian order  */
   %<bitfield>?ab...    select from array of values in big endian order.  */
 
 
static const struct opcode32 neon_opcodes[] =
static const struct opcode32 neon_opcodes[] =
{
{
  /* Extract */
  /* Extract.  */
  {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
  {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
  {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
  {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 
 
  /* Move data element to all lanes */
  /* Move data element to all lanes.  */
  {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
  {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
  {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
  {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
  {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
  {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
 
 
  /* Table lookup */
  /* Table lookup.  */
  {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
 
 
  /* Two registers, miscellaneous */
  /* Half-precision conversions.  */
 
  {FPU_NEON_FP16,   0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
 
  {FPU_NEON_FP16,   0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
 
 
 
  /* Two registers, miscellaneous.  */
  {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
Line 537... Line 553...
  {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
 
 
  /* Three registers of the same length */
  /* Three registers of the same length.  */
  {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
Line 592... Line 608...
  {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
  {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 
 
  /* One register and an immediate value */
  /* One register and an immediate value.  */
  {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
Line 607... Line 623...
  {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
  {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
 
 
  /* Two registers and a shift amount */
  /* Two registers and a shift amount.  */
  {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
  {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
  {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
  {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
  {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
  {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
  {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
  {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
  {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
  {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
Line 643... Line 659...
  {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
  {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
  {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
  {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
  {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
  {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
  {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
  {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
  {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
  {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
  {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
  {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
  {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
  {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
  {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
  {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
  {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
Line 667... Line 683...
  {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
  {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
  {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
  {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
  {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
  {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
  {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
  {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
 
 
  /* Three registers of different lengths */
  /* Three registers of different lengths.  */
  {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
  {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
  {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
  {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
  {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
Line 686... Line 702...
  {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
  {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 
 
  /* Two registers and a scalar */
  /* Two registers and a scalar.  */
  {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
Line 710... Line 726...
  {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
  {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
  {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
  {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 
 
  /* Element and structure load/store */
  /* Element and structure load/store.  */
  {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
  {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
  {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
  {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
  {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
  {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
  {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
  {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
  {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
  {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
Line 772... Line 788...
   %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.  */
   %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.  */
 
 
static const struct opcode32 arm_opcodes[] =
static const struct opcode32 arm_opcodes[] =
{
{
  /* ARM instructions.  */
  /* ARM instructions.  */
  {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
  {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
  {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
  {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
  {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"},
  {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"},
  {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
  {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
  {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"},
  {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"},
  {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
  {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
Line 981... Line 997...
  {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
  {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
  {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15r, %0-3r, %16-19r"},
  {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15r, %0-3r, %16-19r"},
  {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
  {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
 
 
  /* ARM Instructions.  */
  /* ARM Instructions.  */
  {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"},
  {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
  {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"},
  {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"},
  {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"},
  {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"},
  {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15r, %a"},
  {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15r, %a"},
  {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15r, %s"},
  {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15r, %s"},
  {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15r, %s"},
  {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15r, %s"},
 
 
 
  {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15r, %16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15r, %16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15r, %16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15r, %16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15r, %16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15r, %16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15r, %16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15r, %16-19r, %o"},
 
 
  {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
  {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
  {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
  {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
  {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%p%c\t%16-19r, %o"},
 
  {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%p%c\t%16-19r, %o"},
  {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
  {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%p%c\t%16-19r, %o"},
  {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
  {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%p%c\t%16-19r, %o"},
  {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19r, %o"},
  {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
 
 
  {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
 
  {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
 
  {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
 
  {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
 
  {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
 
  {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
 
  {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19r, %o"},
 
 
 
  {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15r, %16-19r, %o"},
 
 
  {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
  {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
  {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
  {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
  {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"},
  {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"},
  {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"},
  {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"},
  {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"},
  {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"},
  {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
  {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
  {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"},
  {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"},
  {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
 
  {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"},
  {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
  {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"},
  {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15r, %16-19r, %o"},
  {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"},
 
  {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"},
  {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
  {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
  {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
 
  {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15r, %o"},
 
 
 
  {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
  {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
  {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
  {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"},
  {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"},
  {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
  {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
  {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"},
  {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"},
  {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
  {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
Line 1024... Line 1092...
  {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
  {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
  {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
  {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
  {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
  {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
 
 
  /* The rest.  */
  /* The rest.  */
  {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
  {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
  {0, 0x00000000, 0x00000000, 0}
  {0, 0x00000000, 0x00000000, 0}
};
};
 
 
/* print_insn_thumb16 recognizes the following format control codes:
/* print_insn_thumb16 recognizes the following format control codes:
 
 
Line 1089... Line 1157...
  /* ARM V5 ISA extends Thumb.  */
  /* ARM V5 ISA extends Thumb.  */
  {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
  {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
  /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
  /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
  {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"},      /* note: 4 bit register number.  */
  {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"},      /* note: 4 bit register number.  */
  /* ARM V4T ISA (Thumb v1).  */
  /* ARM V4T ISA (Thumb v1).  */
  {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"},
  {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
  /* Format 4.  */
  /* Format 4.  */
  {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
  {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
  {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
  {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
  {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
  {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
  {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
  {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
Line 1140... Line 1208...
  {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
  {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
  {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
  {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
  {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
  {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
  {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
  {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
  /* format 6 */
  /* format 6 */
  {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
  {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
  /* format 9 */
  /* format 9 */
  {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
  {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
  {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
  {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
  {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
  {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
  {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
  {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
Line 1153... Line 1221...
  {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
  {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
  /* format 11 */
  /* format 11 */
  {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
  {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
  {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
  {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
  /* format 12 */
  /* format 12 */
  {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"},
  {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
  {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
  {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
  /* format 15 */
  /* format 15 */
  {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
  {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
  {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"},
  {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"},
  /* format 17 */
  /* format 17 */
  {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
  {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
  /* format 16 */
  /* format 16 */
  {ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"},
  {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
  {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
  {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
  /* format 18 */
  /* format 18 */
  {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
  {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
 
 
  /* The E800 .. FFFF range is unconditionally redirected to the
  /* The E800 .. FFFF range is unconditionally redirected to the
     32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
     32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
     are processed via that table.  Thus, we can never encounter a
     are processed via that table.  Thus, we can never encounter a
     bare "second half of BL/BLX(1)" instruction here.  */
     bare "second half of BL/BLX(1)" instruction here.  */
  {ARM_EXT_V1,  0x0000, 0x0000, "undefined"},
  {ARM_EXT_V1,  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
  {0, 0, 0, 0}
  {0, 0, 0, 0}
};
};
 
 
/* Thumb32 opcodes use the same table structure as the ARM opcodes.
/* Thumb32 opcodes use the same table structure as the ARM opcodes.
   We adopt the convention that hw1 is the high 16 bits of .value and
   We adopt the convention that hw1 is the high 16 bits of .value and
Line 1237... Line 1305...
  /* Instructions defined in the basic V6T2 set.  */
  /* Instructions defined in the basic V6T2 set.  */
  {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
  {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
  {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
  {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
  {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
  {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
  {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
  {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
  {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"},
  {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
  {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
  {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
 
 
  {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
  {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
  {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
  {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
  {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
  {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
Line 1272... Line 1340...
  {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
  {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
  {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
  {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
  {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
  {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
Line 1424... Line 1492...
  /* These have been 32-bit since the invention of Thumb.  */
  /* These have been 32-bit since the invention of Thumb.  */
  {ARM_EXT_V4T,  0xf000c000, 0xf800d000, "blx%c\t%B%x"},
  {ARM_EXT_V4T,  0xf000c000, 0xf800d000, "blx%c\t%B%x"},
  {ARM_EXT_V4T,  0xf000d000, 0xf800d000, "bl%c\t%B%x"},
  {ARM_EXT_V4T,  0xf000d000, 0xf800d000, "bl%c\t%B%x"},
 
 
  /* Fallback.  */
  /* Fallback.  */
  {ARM_EXT_V1,   0x00000000, 0x00000000, "undefined"},
  {ARM_EXT_V1,   0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
  {0, 0, 0, 0}
  {0, 0, 0, 0}
};
};
 
 
static const char *const arm_conditional[] =
static const char *const arm_conditional[] =
{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
Line 1500... Line 1568...
/* The address of the insn for which the IT state is valid.  */
/* The address of the insn for which the IT state is valid.  */
static bfd_vma ifthen_address;
static bfd_vma ifthen_address;
#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
 
 
/* Cached mapping symbol state.  */
/* Cached mapping symbol state.  */
enum map_type {
enum map_type
 
{
  MAP_ARM,
  MAP_ARM,
  MAP_THUMB,
  MAP_THUMB,
  MAP_DATA
  MAP_DATA
};
};
 
 
Line 1527... Line 1596...
  regname_selected = option;
  regname_selected = option;
  return old;
  return old;
}
}
 
 
int
int
get_arm_regnames (int option, const char **setname, const char **setdescription,
get_arm_regnames (int option,
 
                  const char **setname,
 
                  const char **setdescription,
                  const char *const **register_names)
                  const char *const **register_names)
{
{
  *setname = regnames[option].name;
  *setname = regnames[option].name;
  *setdescription = regnames[option].description;
  *setdescription = regnames[option].description;
  *register_names = regnames[option].reg_names;
  *register_names = regnames[option].reg_names;
Line 1542... Line 1613...
   Returns pointer to following character of the format string and
   Returns pointer to following character of the format string and
   fills in *VALUEP and *WIDTHP with the extracted value and number of
   fills in *VALUEP and *WIDTHP with the extracted value and number of
   bits extracted.  WIDTHP can be NULL. */
   bits extracted.  WIDTHP can be NULL. */
 
 
static const char *
static const char *
arm_decode_bitfield (const char *ptr, unsigned long insn,
arm_decode_bitfield (const char *ptr,
                     unsigned long *valuep, int *widthp)
                     unsigned long insn,
 
                     unsigned long *valuep,
 
                     int *widthp)
{
{
  unsigned long value = 0;
  unsigned long value = 0;
  int width = 0;
  int width = 0;
 
 
  do
  do
Line 1575... Line 1648...
  return ptr - 1;
  return ptr - 1;
}
}
 
 
static void
static void
arm_decode_shift (long given, fprintf_ftype func, void *stream,
arm_decode_shift (long given, fprintf_ftype func, void *stream,
                  int print_shift)
                  bfd_boolean print_shift)
{
{
  func (stream, "%s", arm_regnames[given & 0xf]);
  func (stream, "%s", arm_regnames[given & 0xf]);
 
 
  if ((given & 0xff0) != 0)
  if ((given & 0xff0) != 0)
    {
    {
Line 1602... Line 1675...
          if (print_shift)
          if (print_shift)
            func (stream, ", %s #%d", arm_shift[shift], amount);
            func (stream, ", %s #%d", arm_shift[shift], amount);
          else
          else
            func (stream, ", #%d", amount);
            func (stream, ", #%d", amount);
        }
        }
 
      else if ((given & 0x80) == 0x80)
 
        func (stream, ", <illegal shifter operand>");
      else if (print_shift)
      else if (print_shift)
        func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
        func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
              arm_regnames[(given & 0xf00) >> 8]);
              arm_regnames[(given & 0xf00) >> 8]);
      else
      else
        func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
        func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
Line 1615... Line 1690...
/* Print one coprocessor instruction on INFO->STREAM.
/* Print one coprocessor instruction on INFO->STREAM.
   Return TRUE if the instuction matched, FALSE if this is not a
   Return TRUE if the instuction matched, FALSE if this is not a
   recognised coprocessor instruction.  */
   recognised coprocessor instruction.  */
 
 
static bfd_boolean
static bfd_boolean
print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
print_insn_coprocessor (bfd_vma pc,
 
                        struct disassemble_info *info,
 
                        long given,
                        bfd_boolean thumb)
                        bfd_boolean thumb)
{
{
  const struct opcode32 *insn;
  const struct opcode32 *insn;
  void *stream = info->stream;
  void *stream = info->stream;
  fprintf_ftype func = info->fprintf_func;
  fprintf_ftype func = info->fprintf_func;
  unsigned long mask;
  unsigned long mask;
  unsigned long value;
  unsigned long value;
 
  unsigned long allowed_arches = ((arm_feature_set *) info->private_data)->coproc;
  int cond;
  int cond;
 
 
  for (insn = coprocessor_opcodes; insn->assembler; insn++)
  for (insn = coprocessor_opcodes; insn->assembler; insn++)
    {
    {
      if (insn->value == FIRST_IWMMXT_INSN
      signed long value_in_comment = 0;
          && info->mach != bfd_mach_arm_XScale
      const char *c;
 
 
 
      if (insn->arch == 0)
 
        switch (insn->value)
 
          {
 
          case SENTINEL_IWMMXT_START:
 
            if (info->mach != bfd_mach_arm_XScale
          && info->mach != bfd_mach_arm_iWMMXt
          && info->mach != bfd_mach_arm_iWMMXt
          && info->mach != bfd_mach_arm_iWMMXt2)
          && info->mach != bfd_mach_arm_iWMMXt2)
        insn = insn + IWMMXT_INSN_COUNT;
              do
 
                insn++;
 
              while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
 
            continue;
 
 
 
          case SENTINEL_IWMMXT_END:
 
            continue;
 
 
 
          case SENTINEL_GENERIC_START:
 
            allowed_arches = ((arm_feature_set *) info->private_data)->core;
 
            continue;
 
 
 
          default:
 
            abort ();
 
          }
 
 
      mask = insn->mask;
      mask = insn->mask;
      value = insn->value;
      value = insn->value;
      if (thumb)
      if (thumb)
        {
        {
Line 1663... Line 1761...
              cond = (given >> 28) & 0xf;
              cond = (given >> 28) & 0xf;
              if (cond == 0xe)
              if (cond == 0xe)
                cond = 16;
                cond = 16;
            }
            }
        }
        }
      if ((given & mask) == value)
 
        {
      if ((given & mask) != value)
          const char *c;
        continue;
 
 
 
      if ((insn->arch & allowed_arches) == 0)
 
        continue;
 
 
          for (c = insn->assembler; *c; c++)
          for (c = insn->assembler; *c; c++)
            {
            {
              if (*c == '%')
              if (*c == '%')
                {
                {
Line 1678... Line 1779...
                    case '%':
                    case '%':
                      func (stream, "%%");
                      func (stream, "%%");
                      break;
                      break;
 
 
                    case 'A':
                    case 'A':
 
                  {
 
                    int offset = given & 0xff;
 
 
                      func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
                      func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
 
 
 
                    value_in_comment = offset * 4;
 
                    if ((given & 0x00800000) == 0)
 
                      value_in_comment = - value_in_comment;
 
 
                      if ((given & (1 << 24)) != 0)
                      if ((given & (1 << 24)) != 0)
                        {
                        {
                          int offset = given & 0xff;
 
 
 
                          if (offset)
                          if (offset)
                            func (stream, ", #%s%d]%s",
                          func (stream, ", #%d]%s",
                                  ((given & 0x00800000) == 0 ? "-" : ""),
                                value_in_comment,
                                  offset * 4,
 
                                  ((given & 0x00200000) != 0 ? "!" : ""));
                                  ((given & 0x00200000) != 0 ? "!" : ""));
                          else
                          else
                            func (stream, "]");
                            func (stream, "]");
                        }
                        }
                      else
                      else
                        {
                        {
                          int offset = given & 0xff;
 
 
 
                          func (stream, "]");
                          func (stream, "]");
 
 
                          if (given & (1 << 21))
                          if (given & (1 << 21))
                            {
                            {
                              if (offset)
                              if (offset)
                                func (stream, ", #%s%d",
                              func (stream, ", #%d", value_in_comment);
                                      ((given & 0x00800000) == 0 ? "-" : ""),
 
                                      offset * 4);
 
                            }
                            }
                          else
                          else
 
                          {
                            func (stream, ", {%d}", offset);
                            func (stream, ", {%d}", offset);
 
                            value_in_comment = offset;
 
                          }
 
                      }
                        }
                        }
                      break;
                      break;
 
 
                    case 'B':
                    case 'B':
                      {
                      {
Line 1737... Line 1842...
                        if (offset)
                        if (offset)
                          {
                          {
                            if (!add)
                            if (!add)
                              offset = -offset;
                              offset = -offset;
                            func (stream, ", #%d", offset);
                            func (stream, ", #%d", offset);
 
                        if (rn != 15)
 
                          value_in_comment = offset;
                          }
                          }
                        func (stream, "]");
                        func (stream, "]");
                        if (rn == 15)
                        if (rn == 15)
                          {
                          {
                            func (stream, "\t; ");
                            func (stream, "\t; ");
Line 1807... Line 1914...
                        default:
                        default:
                          func (stream, _("<illegal precision>"));
                          func (stream, _("<illegal precision>"));
                          break;
                          break;
                        }
                        }
                      break;
                      break;
 
 
                    case 'Q':
                    case 'Q':
                      switch (given & 0x00408000)
                      switch (given & 0x00408000)
                        {
                        {
                        case 0:
                        case 0:
                          func (stream, "s");
                          func (stream, "s");
Line 1824... Line 1932...
                        default:
                        default:
                          func (stream, "p");
                          func (stream, "p");
                          break;
                          break;
                        }
                        }
                      break;
                      break;
 
 
                    case 'R':
                    case 'R':
                      switch (given & 0x60)
                      switch (given & 0x60)
                        {
                        {
                        case 0:
                        case 0:
                          break;
                          break;
Line 1865... Line 1974...
                            else
                            else
                              func (stream, "q%ld", value >> 1);
                              func (stream, "q%ld", value >> 1);
                            break;
                            break;
                          case 'd':
                          case 'd':
                            func (stream, "%ld", value);
                            func (stream, "%ld", value);
 
                        value_in_comment = value;
                            break;
                            break;
                          case 'k':
                          case 'k':
                            {
                            {
                              int from = (given & (1 << 7)) ? 32 : 16;
                              int from = (given & (1 << 7)) ? 32 : 16;
                              func (stream, "%ld", from - value);
                              func (stream, "%ld", from - value);
Line 1895... Line 2005...
                          case 'G':
                          case 'G':
                            func (stream, "%s", iwmmxt_cregnames[value]);
                            func (stream, "%s", iwmmxt_cregnames[value]);
                            break;
                            break;
 
 
                          case 'x':
                          case 'x':
                            func (stream, "0x%lx", value);
                        func (stream, "0x%lx", (value & 0xffffffffUL));
                            break;
                            break;
 
 
                          case '`':
                          case '`':
                            c++;
                            c++;
                            if (value == 0)
                            if (value == 0)
Line 1926... Line 2036...
                          int regno;
                          int regno;
 
 
                          switch (*c)
                          switch (*c)
                            {
                            {
                            case '4': /* Sm pair */
                            case '4': /* Sm pair */
                              func (stream, "{");
 
                              /* Fall through.  */
 
                            case '0': /* Sm, Dm */
                            case '0': /* Sm, Dm */
                              regno = given & 0x0000000f;
                              regno = given & 0x0000000f;
                              if (single)
                              if (single)
                                {
                                {
                                  regno <<= 1;
                                  regno <<= 1;
Line 1996... Line 2104...
                                }
                                }
 
 
                              func (stream, "}");
                              func (stream, "}");
                            }
                            }
                          else if (*c == '4')
                          else if (*c == '4')
                            func (stream, ", %c%d}", single ? 's' : 'd',
                        func (stream, ", %c%d", single ? 's' : 'd',
                                  regno + 1);
                                  regno + 1);
                        }
                        }
                        break;
                        break;
 
 
                      case 'L':
                      case 'L':
Line 2032... Line 2140...
                          int offset = given & 0xff;
                          int offset = given & 0xff;
                          int multiplier = (given & 0x00000100) ? 4 : 1;
                          int multiplier = (given & 0x00000100) ? 4 : 1;
 
 
                          func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
                          func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
 
 
 
                      if (multiplier > 1)
 
                        {
 
                          value_in_comment = offset * multiplier;
 
                          if ((given & 0x00800000) == 0)
 
                            value_in_comment = - value_in_comment;
 
                        }
 
 
                          if (offset)
                          if (offset)
                            {
                            {
                              if ((given & 0x01000000) != 0)
                              if ((given & 0x01000000) != 0)
                                func (stream, ", #%s%d]%s",
                                func (stream, ", #%s%d]%s",
                                      ((given & 0x00800000) == 0 ? "-" : ""),
                                      ((given & 0x00800000) == 0 ? "-" : ""),
Line 2060... Line 2175...
                          const char *rn = arm_regnames [(given >> 16) & 0xf];
                          const char *rn = arm_regnames [(given >> 16) & 0xf];
 
 
                          switch (puw_bits)
                          switch (puw_bits)
                            {
                            {
                            case 1:
                            case 1:
                              /* fall through */
 
                            case 3:
                            case 3:
                              func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
                              func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
                              if (imm4)
                              if (imm4)
                                func (stream, ", lsl #%d", imm4);
                                func (stream, ", lsl #%d", imm4);
                              break;
                              break;
 
 
                            case 4:
                            case 4:
                              /* fall through */
 
                            case 5:
                            case 5:
                              /* fall through */
 
                            case 6:
                            case 6:
                              /* fall through */
 
                            case 7:
                            case 7:
                              func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
                              func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
                              if (imm4 > 0)
                              if (imm4 > 0)
                                func (stream, ", lsl #%d", imm4);
                                func (stream, ", lsl #%d", imm4);
                              func (stream, "]");
                              func (stream, "]");
Line 2104... Line 2215...
                    }
                    }
                }
                }
              else
              else
                func (stream, "%c", *c);
                func (stream, "%c", *c);
            }
            }
 
 
 
      if (value_in_comment > 32 || value_in_comment < -16)
 
        func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
 
 
          return TRUE;
          return TRUE;
        }
        }
    }
 
  return FALSE;
  return FALSE;
}
}
 
 
static void
/* Decodes and prints ARM addressing modes.  Returns the offset
 
   used in the address, if any, if it is worthwhile printing the
 
   offset as a hexadecimal value in a comment at the end of the
 
   line of disassembly.  */
 
 
 
static signed long
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
{
  void *stream = info->stream;
  void *stream = info->stream;
  fprintf_ftype func = info->fprintf_func;
  fprintf_ftype func = info->fprintf_func;
 
  int offset = 0;
 
 
  if (((given & 0x000f0000) == 0x000f0000)
  if (((given & 0x000f0000) == 0x000f0000)
      && ((given & 0x02000000) == 0))
      && ((given & 0x02000000) == 0))
    {
    {
      int offset = given & 0xfff;
      offset = given & 0xfff;
 
 
      func (stream, "[pc");
      func (stream, "[pc");
 
 
      if (given & 0x01000000)
      if (given & 0x01000000)
        {
        {
Line 2151... Line 2271...
          offset = pc + 8;
          offset = pc + 8;
        }
        }
 
 
      func (stream, "\t; ");
      func (stream, "\t; ");
      info->print_address_func (offset, info);
      info->print_address_func (offset, info);
 
      offset = 0;
    }
    }
  else
  else
    {
    {
      func (stream, "[%s",
      func (stream, "[%s",
            arm_regnames[(given >> 16) & 0xf]);
            arm_regnames[(given >> 16) & 0xf]);
      if ((given & 0x01000000) != 0)
      if ((given & 0x01000000) != 0)
        {
        {
          if ((given & 0x02000000) == 0)
          if ((given & 0x02000000) == 0)
            {
            {
              int offset = given & 0xfff;
              offset = given & 0xfff;
              if (offset)
              if (offset)
                func (stream, ", #%s%d",
                func (stream, ", #%s%d",
                      (((given & 0x00800000) == 0)
                      (((given & 0x00800000) == 0)
                       ? "-" : ""), offset);
                       ? "-" : ""), offset);
            }
            }
          else
          else
            {
            {
              func (stream, ", %s",
              func (stream, ", %s",
                    (((given & 0x00800000) == 0)
                    (((given & 0x00800000) == 0)
                     ? "-" : ""));
                     ? "-" : ""));
              arm_decode_shift (given, func, stream, 1);
              arm_decode_shift (given, func, stream, TRUE);
            }
            }
 
 
          func (stream, "]%s",
          func (stream, "]%s",
                ((given & 0x00200000) != 0) ? "!" : "");
                ((given & 0x00200000) != 0) ? "!" : "");
        }
        }
      else
      else
        {
        {
          if ((given & 0x02000000) == 0)
          if ((given & 0x02000000) == 0)
            {
            {
              int offset = given & 0xfff;
              offset = given & 0xfff;
              if (offset)
              if (offset)
                func (stream, "], #%s%d",
                func (stream, "], #%s%d",
                      (((given & 0x00800000) == 0)
                      (((given & 0x00800000) == 0)
                       ? "-" : ""), offset);
                       ? "-" : ""), offset);
              else
              else
Line 2194... Line 2315...
          else
          else
            {
            {
              func (stream, "], %s",
              func (stream, "], %s",
                    (((given & 0x00800000) == 0)
                    (((given & 0x00800000) == 0)
                     ? "-" : ""));
                     ? "-" : ""));
              arm_decode_shift (given, func, stream, 1);
              arm_decode_shift (given, func, stream, TRUE);
            }
            }
        }
        }
    }
    }
 
 
 
  return (signed long) offset;
}
}
 
 
/* Print one neon instruction on INFO->STREAM.
/* Print one neon instruction on INFO->STREAM.
   Return TRUE if the instuction matched, FALSE if this is not a
   Return TRUE if the instuction matched, FALSE if this is not a
   recognised neon instruction.  */
   recognised neon instruction.  */
Line 2215... Line 2338...
 
 
  if (thumb)
  if (thumb)
    {
    {
      if ((given & 0xef000000) == 0xef000000)
      if ((given & 0xef000000) == 0xef000000)
        {
        {
          /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
          /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
          unsigned long bit28 = given & (1 << 28);
          unsigned long bit28 = given & (1 << 28);
 
 
          given &= 0x00ffffff;
          given &= 0x00ffffff;
          if (bit28)
          if (bit28)
            given |= 0xf3000000;
            given |= 0xf3000000;
Line 2234... Line 2357...
 
 
  for (insn = neon_opcodes; insn->assembler; insn++)
  for (insn = neon_opcodes; insn->assembler; insn++)
    {
    {
      if ((given & insn->mask) == insn->value)
      if ((given & insn->mask) == insn->value)
        {
        {
 
          signed long value_in_comment = 0;
          const char *c;
          const char *c;
 
 
          for (c = insn->assembler; *c; c++)
          for (c = insn->assembler; *c; c++)
            {
            {
              if (*c == '%')
              if (*c == '%')
Line 2426... Line 2550...
                        func (stream, "d%d[%d]", reg, ix);
                        func (stream, "d%d[%d]", reg, ix);
                      }
                      }
                      break;
                      break;
 
 
                    case 'E':
                    case 'E':
                      /* Neon encoded constant for mov, mvn, vorr, vbic */
                      /* Neon encoded constant for mov, mvn, vorr, vbic.  */
                      {
                      {
                        int bits = 0;
                        int bits = 0;
                        int cmode = (given >> 8) & 0xf;
                        int cmode = (given >> 8) & 0xf;
                        int op = (given >> 5) & 0x1;
                        int op = (given >> 5) & 0x1;
                        unsigned long value = 0, hival = 0;
                        unsigned long value = 0, hival = 0;
Line 2463... Line 2587...
                          }
                          }
                        else if (cmode == 14)
                        else if (cmode == 14)
                          {
                          {
                            if (op)
                            if (op)
                              {
                              {
                                /* bit replication into bytes */
                                /* Bit replication into bytes.  */
                                int ix;
                                int ix;
                                unsigned long mask;
                                unsigned long mask;
 
 
                                value = 0;
                                value = 0;
                                hival = 0;
                                hival = 0;
Line 2481... Line 2605...
                                  }
                                  }
                                size = 64;
                                size = 64;
                              }
                              }
                            else
                            else
                              {
                              {
                                /* byte replication */
                                /* Byte replication.  */
                                value = (unsigned long)bits;
                                value = (unsigned long)bits;
                                size = 8;
                                size = 8;
                              }
                              }
                          }
                          }
                        else if (!op)
                        else if (!op)
                          {
                          {
                            /* floating point encoding */
                            /* Floating point encoding.  */
                            int tmp;
                            int tmp;
 
 
                            value = (unsigned long)(bits & 0x7f) << 19;
                            value = (unsigned long)(bits & 0x7f) << 19;
                            value |= (unsigned long)(bits & 0x80) << 24;
                            value |= (unsigned long)(bits & 0x80) << 24;
                            tmp = bits & 0x40 ? 0x3c : 0x40;
                            tmp = bits & 0x40 ? 0x3c : 0x40;
Line 2581... Line 2705...
                          case 'r':
                          case 'r':
                            func (stream, "%s", arm_regnames[value]);
                            func (stream, "%s", arm_regnames[value]);
                            break;
                            break;
                          case 'd':
                          case 'd':
                            func (stream, "%ld", value);
                            func (stream, "%ld", value);
 
                            value_in_comment = value;
                            break;
                            break;
                          case 'e':
                          case 'e':
                            func (stream, "%ld", (1ul << width) - value);
                            func (stream, "%ld", (1ul << width) - value);
                            break;
                            break;
 
 
                          case 'S':
                          case 'S':
                          case 'T':
                          case 'T':
                          case 'U':
                          case 'U':
                            /* various width encodings */
                            /* Various width encodings.  */
                            {
                            {
                              int base = 8 << (*c - 'S'); /* 8,16 or 32 */
                              int base = 8 << (*c - 'S'); /* 8,16 or 32 */
                              int limit;
                              int limit;
                              unsigned low, high;
                              unsigned low, high;
 
 
Line 2653... Line 2778...
                    }
                    }
                }
                }
              else
              else
                func (stream, "%c", *c);
                func (stream, "%c", *c);
            }
            }
 
 
 
          if (value_in_comment > 32 || value_in_comment < -16)
 
            func (stream, "\t; 0x%lx", value_in_comment);
 
 
          return TRUE;
          return TRUE;
        }
        }
    }
    }
  return FALSE;
  return FALSE;
}
}
Line 2676... Line 2805...
  if (print_insn_neon (info, given, FALSE))
  if (print_insn_neon (info, given, FALSE))
    return;
    return;
 
 
  for (insn = arm_opcodes; insn->assembler; insn++)
  for (insn = arm_opcodes; insn->assembler; insn++)
    {
    {
      if (insn->value == FIRST_IWMMXT_INSN
      if ((given & insn->mask) != insn->value)
          && info->mach != bfd_mach_arm_XScale
        continue;
          && info->mach != bfd_mach_arm_iWMMXt)
 
        insn = insn + IWMMXT_INSN_COUNT;
      if ((insn->arch & ((arm_feature_set *) info->private_data)->core) == 0)
 
        continue;
 
 
      if ((given & insn->mask) == insn->value
 
          /* Special case: an instruction with all bits set in the condition field
          /* Special case: an instruction with all bits set in the condition field
             (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
             (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
             or by the catchall at the end of the table.  */
             or by the catchall at the end of the table.  */
          && ((given & 0xF0000000) != 0xF0000000
      if ((given & 0xF0000000) != 0xF0000000
              || (insn->mask & 0xF0000000) == 0xF0000000
              || (insn->mask & 0xF0000000) == 0xF0000000
              || (insn->mask == 0 && insn->value == 0)))
          || (insn->mask == 0 && insn->value == 0))
        {
        {
 
          signed long value_in_comment = 0;
          const char *c;
          const char *c;
 
 
          for (c = insn->assembler; *c; c++)
          for (c = insn->assembler; *c; c++)
            {
            {
              if (*c == '%')
              if (*c == '%')
Line 2702... Line 2832...
                    case '%':
                    case '%':
                      func (stream, "%%");
                      func (stream, "%%");
                      break;
                      break;
 
 
                    case 'a':
                    case 'a':
                      print_arm_address (pc, info, given);
                      value_in_comment = print_arm_address (pc, info, given);
                      break;
                      break;
 
 
                    case 'P':
                    case 'P':
                      /* Set P address bit and use normal address
                      /* Set P address bit and use normal address
                         printing routine.  */
                         printing routine.  */
                      print_arm_address (pc, info, given | (1 << 24));
                      value_in_comment = print_arm_address (pc, info, given | (1 << 24));
                      break;
                      break;
 
 
                    case 's':
                    case 's':
                      if ((given & 0x004f0000) == 0x004f0000)
                      if ((given & 0x004f0000) == 0x004f0000)
                        {
                        {
Line 2725... Line 2855...
                          func (stream, "[pc, #%d]\t; ", offset);
                          func (stream, "[pc, #%d]\t; ", offset);
                          info->print_address_func (offset + pc + 8, info);
                          info->print_address_func (offset + pc + 8, info);
                        }
                        }
                      else
                      else
                        {
                        {
 
                          bfd_boolean negative = (given & 0x00800000) == 0;
 
                          int offset = ((given & 0xf00) >> 4) | (given & 0xf);
 
 
 
                          if (negative)
 
                            offset = -offset;
 
 
                          func (stream, "[%s",
                          func (stream, "[%s",
                                arm_regnames[(given >> 16) & 0xf]);
                                arm_regnames[(given >> 16) & 0xf]);
 
 
                          if ((given & 0x01000000) != 0)
                          if ((given & 0x01000000) != 0)
                            {
                            {
                              /* Pre-indexed.  */
                              /* Pre-indexed.  */
                              if ((given & 0x00400000) == 0x00400000)
                              if ((given & 0x00400000) == 0x00400000)
                                {
                                {
                                  /* Immediate.  */
                                  /* Immediate.  */
                                  int offset = ((given & 0xf00) >> 4) | (given & 0xf);
 
                                  if (offset)
                                  if (offset)
                                    func (stream, ", #%s%d",
                                    func (stream, ", #%d", offset);
                                          (((given & 0x00800000) == 0)
                                  value_in_comment = offset;
                                           ? "-" : ""), offset);
 
                                }
                                }
                              else
                              else
                                {
                                {
                                  /* Register.  */
                                  /* Register.  */
                                  func (stream, ", %s%s",
                                  func (stream, ", %s%s", negative ? "-" : "",
                                        (((given & 0x00800000) == 0)
 
                                         ? "-" : ""),
 
                                        arm_regnames[given & 0xf]);
                                        arm_regnames[given & 0xf]);
                                }
                                }
 
 
                              func (stream, "]%s",
                              func (stream, "]%s",
                                    ((given & 0x00200000) != 0) ? "!" : "");
                                    ((given & 0x00200000) != 0) ? "!" : "");
Line 2757... Line 2890...
                            {
                            {
                              /* Post-indexed.  */
                              /* Post-indexed.  */
                              if ((given & 0x00400000) == 0x00400000)
                              if ((given & 0x00400000) == 0x00400000)
                                {
                                {
                                  /* Immediate.  */
                                  /* Immediate.  */
                                  int offset = ((given & 0xf00) >> 4) | (given & 0xf);
 
                                  if (offset)
                                  if (offset)
                                    func (stream, "], #%s%d",
                                    func (stream, "], #%d", offset);
                                          (((given & 0x00800000) == 0)
 
                                           ? "-" : ""), offset);
 
                                  else
                                  else
                                    func (stream, "]");
                                    func (stream, "]");
 
 
 
                                  value_in_comment = offset;
                                }
                                }
                              else
                              else
                                {
                                {
                                  /* Register.  */
                                  /* Register.  */
                                  func (stream, "], %s%s",
                                  func (stream, "], %s%s", negative ? "-" : "",
                                        (((given & 0x00800000) == 0)
 
                                         ? "-" : ""),
 
                                        arm_regnames[given & 0xf]);
                                        arm_regnames[given & 0xf]);
                                }
                                }
                            }
                            }
                        }
                        }
                      break;
                      break;
Line 2809... Line 2939...
                        func (stream, "}");
                        func (stream, "}");
                      }
                      }
                      break;
                      break;
 
 
                    case 'q':
                    case 'q':
                      arm_decode_shift (given, func, stream, 0);
                      arm_decode_shift (given, func, stream, FALSE);
                      break;
                      break;
 
 
                    case 'o':
                    case 'o':
                      if ((given & 0x02000000) != 0)
                      if ((given & 0x02000000) != 0)
                        {
                        {
                          int rotate = (given & 0xf00) >> 7;
                          int rotate = (given & 0xf00) >> 7;
                          int immed = (given & 0xff);
                          int immed = (given & 0xff);
 
 
                          immed = (((immed << (32 - rotate))
                          immed = (((immed << (32 - rotate))
                                    | (immed >> rotate)) & 0xffffffff);
                                    | (immed >> rotate)) & 0xffffffff);
                          func (stream, "#%d\t; 0x%x", immed, immed);
                          func (stream, "#%d", immed);
 
                          value_in_comment = immed;
                        }
                        }
                      else
                      else
                        arm_decode_shift (given, func, stream, 1);
                        arm_decode_shift (given, func, stream, TRUE);
                      break;
                      break;
 
 
                    case 'p':
                    case 'p':
                      if ((given & 0x0000f000) == 0x0000f000)
                      if ((given & 0x0000f000) == 0x0000f000)
                        func (stream, "p");
                        func (stream, "p");
Line 2836... Line 2968...
                      if ((given & 0x01200000) == 0x00200000)
                      if ((given & 0x01200000) == 0x00200000)
                        func (stream, "t");
                        func (stream, "t");
                      break;
                      break;
 
 
                    case 'A':
                    case 'A':
 
                      {
 
                        int offset = given & 0xff;
 
 
 
                        value_in_comment = offset * 4;
 
                        if ((given & 0x00800000) == 0)
 
                          value_in_comment = - value_in_comment;
 
 
                      func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
                      func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
 
 
                      if ((given & (1 << 24)) != 0)
                      if ((given & (1 << 24)) != 0)
                        {
                        {
                          int offset = given & 0xff;
 
 
 
                          if (offset)
                          if (offset)
                            func (stream, ", #%s%d]%s",
                              func (stream, ", #%d]%s",
                                  ((given & 0x00800000) == 0 ? "-" : ""),
                                    value_in_comment,
                                  offset * 4,
 
                                  ((given & 0x00200000) != 0 ? "!" : ""));
                                  ((given & 0x00200000) != 0 ? "!" : ""));
                          else
                          else
                            func (stream, "]");
                            func (stream, "]");
                        }
                        }
                      else
                      else
                        {
                        {
                          int offset = given & 0xff;
 
 
 
                          func (stream, "]");
                          func (stream, "]");
 
 
                          if (given & (1 << 21))
                          if (given & (1 << 21))
                            {
                            {
                              if (offset)
                              if (offset)
                                func (stream, ", #%s%d",
                                  func (stream, ", #%d", value_in_comment);
                                      ((given & 0x00800000) == 0 ? "-" : ""),
 
                                      offset * 4);
 
                            }
                            }
                          else
                          else
 
                              {
                            func (stream, ", {%d}", offset);
                            func (stream, ", {%d}", offset);
 
                                value_in_comment = offset;
 
                              }
 
                          }
                        }
                        }
                      break;
                      break;
 
 
                    case 'B':
                    case 'B':
                      /* Print ARM V5 BLX(1) address: pc+25 bits.  */
                      /* Print ARM V5 BLX(1) address: pc+25 bits.  */
Line 2931... Line 3067...
                          case 'r':
                          case 'r':
                            func (stream, "%s", arm_regnames[value]);
                            func (stream, "%s", arm_regnames[value]);
                            break;
                            break;
                          case 'd':
                          case 'd':
                            func (stream, "%ld", value);
                            func (stream, "%ld", value);
 
                            value_in_comment = value;
                            break;
                            break;
                          case 'b':
                          case 'b':
                            func (stream, "%ld", value * 8);
                            func (stream, "%ld", value * 8);
 
                            value_in_comment = value * 8;
                            break;
                            break;
                          case 'W':
                          case 'W':
                            func (stream, "%ld", value + 1);
                            func (stream, "%ld", value + 1);
 
                            value_in_comment = value + 1;
                            break;
                            break;
                          case 'x':
                          case 'x':
                            func (stream, "0x%08lx", value);
                            func (stream, "0x%08lx", value);
 
 
                            /* Some SWI instructions have special
                            /* Some SWI instructions have special
Line 2950... Line 3089...
                            else if ((given & 0x0fffffff) == 0x0FF00001)
                            else if ((given & 0x0fffffff) == 0x0FF00001)
                              func (stream, "\t; IMBRange");
                              func (stream, "\t; IMBRange");
                            break;
                            break;
                          case 'X':
                          case 'X':
                            func (stream, "%01lx", value & 0xf);
                            func (stream, "%01lx", value & 0xf);
 
                            value_in_comment = value;
                            break;
                            break;
                          case '`':
                          case '`':
                            c++;
                            c++;
                            if (value == 0)
                            if (value == 0)
                              func (stream, "%c", *c);
                              func (stream, "%c", *c);
Line 2976... Line 3116...
                        {
                        {
                          int imm;
                          int imm;
 
 
                          imm = (given & 0xf) | ((given & 0xfff00) >> 4);
                          imm = (given & 0xf) | ((given & 0xfff00) >> 4);
                          func (stream, "%d", imm);
                          func (stream, "%d", imm);
 
                          value_in_comment = imm;
                        }
                        }
                        break;
                        break;
 
 
                      case 'E':
                      case 'E':
                        /* LSB and WIDTH fields of BFI or BFC.  The machine-
                        /* LSB and WIDTH fields of BFI or BFC.  The machine-
                           language instruction encodes LSB and MSB.  */
                           language instruction encodes LSB and MSB.  */
                        {
                        {
                          long msb = (given & 0x001f0000) >> 16;
                          long msb = (given & 0x001f0000) >> 16;
                          long lsb = (given & 0x00000f80) >> 7;
                          long lsb = (given & 0x00000f80) >> 7;
 
 
                          long width = msb - lsb + 1;
                          long width = msb - lsb + 1;
 
 
                          if (width > 0)
                          if (width > 0)
                            func (stream, "#%lu, #%lu", lsb, width);
                            func (stream, "#%lu, #%lu", lsb, width);
                          else
                          else
                            func (stream, "(invalid: %lu:%lu)", lsb, msb);
                            func (stream, "(invalid: %lu:%lu)", lsb, msb);
                        }
                        }
Line 3001... Line 3142...
                           instruction, encoded in bits 0:11 and 15:19.  */
                           instruction, encoded in bits 0:11 and 15:19.  */
                        {
                        {
                          long hi = (given & 0x000f0000) >> 4;
                          long hi = (given & 0x000f0000) >> 4;
                          long lo = (given & 0x00000fff);
                          long lo = (given & 0x00000fff);
                          long imm16 = hi | lo;
                          long imm16 = hi | lo;
                          func (stream, "#%lu\t; 0x%lx", imm16, imm16);
 
 
                          func (stream, "#%lu", imm16);
 
                          value_in_comment = imm16;
                        }
                        }
                        break;
                        break;
 
 
                      default:
                      default:
                        abort ();
                        abort ();
Line 3013... Line 3156...
                    }
                    }
                }
                }
              else
              else
                func (stream, "%c", *c);
                func (stream, "%c", *c);
            }
            }
 
 
 
          if (value_in_comment > 32 || value_in_comment < -16)
 
            func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
          return;
          return;
        }
        }
    }
    }
  abort ();
  abort ();
}
}
Line 3031... Line 3177...
  fprintf_ftype func = info->fprintf_func;
  fprintf_ftype func = info->fprintf_func;
 
 
  for (insn = thumb_opcodes; insn->assembler; insn++)
  for (insn = thumb_opcodes; insn->assembler; insn++)
    if ((given & insn->mask) == insn->value)
    if ((given & insn->mask) == insn->value)
      {
      {
 
        signed long value_in_comment = 0;
        const char *c = insn->assembler;
        const char *c = insn->assembler;
 
 
        for (; *c; c++)
        for (; *c; c++)
          {
          {
            int domaskpc = 0;
            int domaskpc = 0;
            int domasklr = 0;
            int domasklr = 0;
 
 
Line 3203... Line 3351...
                            func (stream, "%s", arm_regnames[reg]);
                            func (stream, "%s", arm_regnames[reg]);
                            break;
                            break;
 
 
                          case 'd':
                          case 'd':
                            func (stream, "%ld", reg);
                            func (stream, "%ld", reg);
 
                            value_in_comment = reg;
                            break;
                            break;
 
 
                          case 'H':
                          case 'H':
                            func (stream, "%ld", reg << 1);
                            func (stream, "%ld", reg << 1);
 
                            value_in_comment = reg << 1;
                            break;
                            break;
 
 
                          case 'W':
                          case 'W':
                            func (stream, "%ld", reg << 2);
                            func (stream, "%ld", reg << 2);
 
                            value_in_comment = reg << 2;
                            break;
                            break;
 
 
                          case 'a':
                          case 'a':
                            /* PC-relative address -- the bottom two
                            /* PC-relative address -- the bottom two
                               bits of the address are dropped
                               bits of the address are dropped
                               before the calculation.  */
                               before the calculation.  */
                            info->print_address_func
                            info->print_address_func
                              (((pc + 4) & ~3) + (reg << 2), info);
                              (((pc + 4) & ~3) + (reg << 2), info);
 
                            value_in_comment = 0;
                            break;
                            break;
 
 
                          case 'x':
                          case 'x':
                            func (stream, "0x%04lx", reg);
                            func (stream, "0x%04lx", reg);
                            break;
                            break;
 
 
                          case 'B':
                          case 'B':
                            reg = ((reg ^ (1 << bitend)) - (1 << bitend));
                            reg = ((reg ^ (1 << bitend)) - (1 << bitend));
                            info->print_address_func (reg * 2 + pc + 4, info);
                            info->print_address_func (reg * 2 + pc + 4, info);
 
                            value_in_comment = 0;
                            break;
                            break;
 
 
                          case 'c':
                          case 'c':
                            func (stream, "%s", arm_conditional [reg]);
                            func (stream, "%s", arm_conditional [reg]);
                            break;
                            break;
Line 3264... Line 3417...
 
 
              default:
              default:
                abort ();
                abort ();
              }
              }
          }
          }
 
 
 
        if (value_in_comment > 32 || value_in_comment < -16)
 
          func (stream, "\t; 0x%lx", value_in_comment);
        return;
        return;
      }
      }
 
 
  /* No match.  */
  /* No match.  */
  abort ();
  abort ();
}
}
 
 
/* Return the name of an V7M special register.  */
/* Return the name of an V7M special register.  */
 
 
static const char *
static const char *
psr_name (int regno)
psr_name (int regno)
{
{
  switch (regno)
  switch (regno)
    {
    {
Line 3313... Line 3470...
    return;
    return;
 
 
  for (insn = thumb32_opcodes; insn->assembler; insn++)
  for (insn = thumb32_opcodes; insn->assembler; insn++)
    if ((given & insn->mask) == insn->value)
    if ((given & insn->mask) == insn->value)
      {
      {
 
        signed long value_in_comment = 0;
        const char *c = insn->assembler;
        const char *c = insn->assembler;
 
 
        for (; *c; c++)
        for (; *c; c++)
          {
          {
            if (*c != '%')
            if (*c != '%')
              {
              {
                func (stream, "%c", *c);
                func (stream, "%c", *c);
Line 3347... Line 3506...
                break;
                break;
 
 
              case 'I':
              case 'I':
                {
                {
                  unsigned int imm12 = 0;
                  unsigned int imm12 = 0;
 
 
                  imm12 |= (given & 0x000000ffu);
                  imm12 |= (given & 0x000000ffu);
                  imm12 |= (given & 0x00007000u) >> 4;
                  imm12 |= (given & 0x00007000u) >> 4;
                  imm12 |= (given & 0x04000000u) >> 15;
                  imm12 |= (given & 0x04000000u) >> 15;
                  func (stream, "#%u\t; 0x%x", imm12, imm12);
                  func (stream, "#%u", imm12);
 
                  value_in_comment = imm12;
                }
                }
                break;
                break;
 
 
              case 'M':
              case 'M':
                {
                {
                  unsigned int bits = 0, imm, imm8, mod;
                  unsigned int bits = 0, imm, imm8, mod;
 
 
                  bits |= (given & 0x000000ffu);
                  bits |= (given & 0x000000ffu);
                  bits |= (given & 0x00007000u) >> 4;
                  bits |= (given & 0x00007000u) >> 4;
                  bits |= (given & 0x04000000u) >> 15;
                  bits |= (given & 0x04000000u) >> 15;
                  imm8 = (bits & 0x0ff);
                  imm8 = (bits & 0x0ff);
                  mod = (bits & 0xf00) >> 8;
                  mod = (bits & 0xf00) >> 8;
Line 3373... Line 3535...
                    default:
                    default:
                      mod  = (bits & 0xf80) >> 7;
                      mod  = (bits & 0xf80) >> 7;
                      imm8 = (bits & 0x07f) | 0x80;
                      imm8 = (bits & 0x07f) | 0x80;
                      imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
                      imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
                    }
                    }
                  func (stream, "#%u\t; 0x%x", imm, imm);
                  func (stream, "#%u", imm);
 
                  value_in_comment = imm;
                }
                }
                break;
                break;
 
 
              case 'J':
              case 'J':
                {
                {
                  unsigned int imm = 0;
                  unsigned int imm = 0;
 
 
                  imm |= (given & 0x000000ffu);
                  imm |= (given & 0x000000ffu);
                  imm |= (given & 0x00007000u) >> 4;
                  imm |= (given & 0x00007000u) >> 4;
                  imm |= (given & 0x04000000u) >> 15;
                  imm |= (given & 0x04000000u) >> 15;
                  imm |= (given & 0x000f0000u) >> 4;
                  imm |= (given & 0x000f0000u) >> 4;
                  func (stream, "#%u\t; 0x%x", imm, imm);
                  func (stream, "#%u", imm);
 
                  value_in_comment = imm;
                }
                }
                break;
                break;
 
 
              case 'K':
              case 'K':
                {
                {
                  unsigned int imm = 0;
                  unsigned int imm = 0;
 
 
                  imm |= (given & 0x000f0000u) >> 16;
                  imm |= (given & 0x000f0000u) >> 16;
                  imm |= (given & 0x00000ff0u) >> 0;
                  imm |= (given & 0x00000ff0u) >> 0;
                  imm |= (given & 0x0000000fu) << 12;
                  imm |= (given & 0x0000000fu) << 12;
                  func (stream, "#%u\t; 0x%x", imm, imm);
                  func (stream, "#%u", imm);
 
                  value_in_comment = imm;
                }
                }
                break;
                break;
 
 
              case 'S':
              case 'S':
                {
                {
Line 3446... Line 3613...
                  unsigned int i8  = (given & 0x000000ff);
                  unsigned int i8  = (given & 0x000000ff);
                  bfd_boolean writeback = FALSE, postind = FALSE;
                  bfd_boolean writeback = FALSE, postind = FALSE;
                  int offset = 0;
                  int offset = 0;
 
 
                  func (stream, "[%s", arm_regnames[Rn]);
                  func (stream, "[%s", arm_regnames[Rn]);
                  if (U) /* 12-bit positive immediate offset */
                  if (U) /* 12-bit positive immediate offset.  */
 
                    {
                    offset = i12;
                    offset = i12;
                  else if (Rn == 15) /* 12-bit negative immediate offset */
                      if (Rn != 15)
 
                        value_in_comment = offset;
 
                    }
 
                  else if (Rn == 15) /* 12-bit negative immediate offset.  */
                    offset = -(int)i12;
                    offset = -(int)i12;
                  else if (op == 0x0) /* shifted register offset */
                  else if (op == 0x0) /* Shifted register offset.  */
                    {
                    {
                      unsigned int Rm = (i8 & 0x0f);
                      unsigned int Rm = (i8 & 0x0f);
                      unsigned int sh = (i8 & 0x30) >> 4;
                      unsigned int sh = (i8 & 0x30) >> 4;
 
 
                      func (stream, ", %s", arm_regnames[Rm]);
                      func (stream, ", %s", arm_regnames[Rm]);
                      if (sh)
                      if (sh)
                        func (stream, ", lsl #%u", sh);
                        func (stream, ", lsl #%u", sh);
                      func (stream, "]");
                      func (stream, "]");
                      break;
                      break;
                    }
                    }
                  else switch (op)
                  else switch (op)
                    {
                    {
                    case 0xE:  /* 8-bit positive immediate offset */
                    case 0xE:  /* 8-bit positive immediate offset.  */
                      offset = i8;
                      offset = i8;
                      break;
                      break;
 
 
                    case 0xC:  /* 8-bit negative immediate offset */
                    case 0xC:  /* 8-bit negative immediate offset.  */
                      offset = -i8;
                      offset = -i8;
                      break;
                      break;
 
 
                    case 0xF:  /* 8-bit + preindex with wb */
                    case 0xF:  /* 8-bit + preindex with wb.  */
                      offset = i8;
                      offset = i8;
                      writeback = TRUE;
                      writeback = TRUE;
                      break;
                      break;
 
 
                    case 0xD:  /* 8-bit - preindex with wb */
                    case 0xD:  /* 8-bit - preindex with wb.  */
                      offset = -i8;
                      offset = -i8;
                      writeback = TRUE;
                      writeback = TRUE;
                      break;
                      break;
 
 
                    case 0xB:  /* 8-bit + postindex */
                    case 0xB:  /* 8-bit + postindex.  */
                      offset = i8;
                      offset = i8;
                      postind = TRUE;
                      postind = TRUE;
                      break;
                      break;
 
 
                    case 0x9:  /* 8-bit - postindex */
                    case 0x9:  /* 8-bit - postindex.  */
                      offset = -i8;
                      offset = -i8;
                      postind = TRUE;
                      postind = TRUE;
                      break;
                      break;
 
 
                    default:
                    default:
Line 3525... Line 3697...
 
 
                  func (stream, "[%s", arm_regnames[Rn]);
                  func (stream, "[%s", arm_regnames[Rn]);
                  if (P)
                  if (P)
                    {
                    {
                      if (off || !U)
                      if (off || !U)
 
                        {
                        func (stream, ", #%c%u", U ? '+' : '-', off * 4);
                        func (stream, ", #%c%u", U ? '+' : '-', off * 4);
 
                          value_in_comment = off * 4 * U ? 1 : -1;
 
                        }
                      func (stream, "]");
                      func (stream, "]");
                      if (W)
                      if (W)
                        func (stream, "!");
                        func (stream, "!");
                    }
                    }
                  else
                  else
                    {
                    {
                      func (stream, "], ");
                      func (stream, "], ");
                      if (W)
                      if (W)
 
                        {
                        func (stream, "#%c%u", U ? '+' : '-', off * 4);
                        func (stream, "#%c%u", U ? '+' : '-', off * 4);
 
                          value_in_comment = off * 4 * U ? 1 : -1;
 
                        }
                      else
                      else
 
                        {
                        func (stream, "{%u}", off);
                        func (stream, "{%u}", off);
 
                          value_in_comment = off;
 
                        }
                    }
                    }
                }
                }
                break;
                break;
 
 
              case 'w':
              case 'w':
                {
                {
                  unsigned int Sbit = (given & 0x01000000) >> 24;
                  unsigned int Sbit = (given & 0x01000000) >> 24;
                  unsigned int type = (given & 0x00600000) >> 21;
                  unsigned int type = (given & 0x00600000) >> 21;
 
 
                  switch (type)
                  switch (type)
                    {
                    {
                    case 0: func (stream, Sbit ? "sb" : "b"); break;
                    case 0: func (stream, Sbit ? "sb" : "b"); break;
                    case 1: func (stream, Sbit ? "sh" : "h"); break;
                    case 1: func (stream, Sbit ? "sh" : "h"); break;
                    case 2:
                    case 2:
Line 3582... Line 3764...
 
 
              case 'E':
              case 'E':
                {
                {
                  unsigned int msb = (given & 0x0000001f);
                  unsigned int msb = (given & 0x0000001f);
                  unsigned int lsb = 0;
                  unsigned int lsb = 0;
 
 
                  lsb |= (given & 0x000000c0u) >> 6;
                  lsb |= (given & 0x000000c0u) >> 6;
                  lsb |= (given & 0x00007000u) >> 10;
                  lsb |= (given & 0x00007000u) >> 10;
                  func (stream, "#%u, #%u", lsb, msb - lsb + 1);
                  func (stream, "#%u, #%u", lsb, msb - lsb + 1);
                }
                }
                break;
                break;
 
 
              case 'F':
              case 'F':
                {
                {
                  unsigned int width = (given & 0x0000001f) + 1;
                  unsigned int width = (given & 0x0000001f) + 1;
                  unsigned int lsb = 0;
                  unsigned int lsb = 0;
 
 
                  lsb |= (given & 0x000000c0u) >> 6;
                  lsb |= (given & 0x000000c0u) >> 6;
                  lsb |= (given & 0x00007000u) >> 10;
                  lsb |= (given & 0x00007000u) >> 10;
                  func (stream, "#%u, #%u", lsb, width);
                  func (stream, "#%u, #%u", lsb, width);
                }
                }
                break;
                break;
Line 3642... Line 3826...
                break;
                break;
 
 
              case 's':
              case 's':
                {
                {
                  unsigned int shift = 0;
                  unsigned int shift = 0;
 
 
                  shift |= (given & 0x000000c0u) >> 6;
                  shift |= (given & 0x000000c0u) >> 6;
                  shift |= (given & 0x00007000u) >> 10;
                  shift |= (given & 0x00007000u) >> 10;
                  if (given & 0x00200000u)
                  if (given & 0x00200000u)
                    func (stream, ", asr #%u", shift);
                    func (stream, ", asr #%u", shift);
                  else if (shift)
                  else if (shift)
Line 3655... Line 3840...
                break;
                break;
 
 
              case 'R':
              case 'R':
                {
                {
                  unsigned int rot = (given & 0x00000030) >> 4;
                  unsigned int rot = (given & 0x00000030) >> 4;
 
 
                  if (rot)
                  if (rot)
                    func (stream, ", ror #%u", rot * 8);
                    func (stream, ", ror #%u", rot * 8);
                }
                }
                break;
                break;
 
 
Line 3709... Line 3895...
 
 
                  c = arm_decode_bitfield (c, given, &val, &width);
                  c = arm_decode_bitfield (c, given, &val, &width);
 
 
                  switch (*c)
                  switch (*c)
                    {
                    {
                    case 'd': func (stream, "%lu", val); break;
                    case 'd':
                    case 'W': func (stream, "%lu", val * 4); break;
                      func (stream, "%lu", val);
 
                      value_in_comment = val;
 
                      break;
 
                    case 'W':
 
                      func (stream, "%lu", val * 4);
 
                      value_in_comment = val * 4;
 
                      break;
                    case 'r': func (stream, "%s", arm_regnames[val]); break;
                    case 'r': func (stream, "%s", arm_regnames[val]); break;
 
 
                    case 'c':
                    case 'c':
                      func (stream, "%s", arm_conditional[val]);
                      func (stream, "%s", arm_conditional[val]);
                      break;
                      break;
Line 3734... Line 3926...
                    case '?':
                    case '?':
                      func (stream, "%c", c[(1 << width) - (int)val]);
                      func (stream, "%c", c[(1 << width) - (int)val]);
                      c += 1 << width;
                      c += 1 << width;
                      break;
                      break;
 
 
 
                    case 'x':
 
                      func (stream, "0x%lx", val & 0xffffffffUL);
 
                      break;
 
 
                    default:
                    default:
                      abort ();
                      abort ();
                    }
                    }
                }
 
                break;
                break;
 
                }
 
 
              default:
              default:
                abort ();
                abort ();
              }
              }
          }
          }
 
 
 
        if (value_in_comment > 32 || value_in_comment < -16)
 
          func (stream, "\t; 0x%lx", value_in_comment);
        return;
        return;
      }
      }
 
 
  /* No match.  */
  /* No match.  */
  abort ();
  abort ();
}
}
 
 
/* Print data bytes on INFO->STREAM.  */
/* Print data bytes on INFO->STREAM.  */
 
 
static void
static void
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info,
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
 
                 struct disassemble_info *info,
                 long given)
                 long given)
{
{
  switch (info->bytes_per_chunk)
  switch (info->bytes_per_chunk)
    {
    {
    case 1:
    case 1:
Line 3850... Line 4050...
    }
    }
}
}
 
 
/* Search back through the insn stream to determine if this instruction is
/* Search back through the insn stream to determine if this instruction is
   conditionally executed.  */
   conditionally executed.  */
 
 
static void
static void
find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
find_ifthen_state (bfd_vma pc,
 
                   struct disassemble_info *info,
                   bfd_boolean little)
                   bfd_boolean little)
{
{
  unsigned char b[2];
  unsigned char b[2];
  unsigned int insn;
  unsigned int insn;
  int status;
  int status;
Line 3930... Line 4132...
 
 
/* Try to infer the code type (Arm or Thumb) from a symbol.
/* Try to infer the code type (Arm or Thumb) from a symbol.
   Returns nonzero if *MAP_TYPE was set.  */
   Returns nonzero if *MAP_TYPE was set.  */
 
 
static int
static int
get_sym_code_type (struct disassemble_info *info, int n,
get_sym_code_type (struct disassemble_info *info,
 
                   int n,
                   enum map_type *map_type)
                   enum map_type *map_type)
{
{
  elf_symbol_type *es;
  elf_symbol_type *es;
  unsigned int type;
  unsigned int type;
  const char *name;
  const char *name;
Line 3961... Line 4164...
    }
    }
 
 
  return FALSE;
  return FALSE;
}
}
 
 
 
/* Given a bfd_mach_arm_XXX value, this function fills in the fields
 
   of the supplied arm_feature_set structure with bitmasks indicating
 
   the support base architectures and coprocessor extensions.
 
 
 
   FIXME: This could more efficiently implemented as a constant array,
 
   although it would also be less robust.  */
 
 
 
static void
 
select_arm_features (unsigned long mach,
 
                     arm_feature_set * features)
 
{
 
#undef  ARM_FEATURE
 
#define ARM_FEATURE(ARCH,CEXT) \
 
  features->core = (ARCH); \
 
  features->coproc = (CEXT) | FPU_FPA; \
 
  return
 
 
 
  switch (mach)
 
    {
 
    case bfd_mach_arm_2:       ARM_ARCH_V2;
 
    case bfd_mach_arm_2a:      ARM_ARCH_V2S;
 
    case bfd_mach_arm_3:       ARM_ARCH_V3;
 
    case bfd_mach_arm_3M:      ARM_ARCH_V3M;
 
    case bfd_mach_arm_4:       ARM_ARCH_V4;
 
    case bfd_mach_arm_4T:      ARM_ARCH_V4T;
 
    case bfd_mach_arm_5:       ARM_ARCH_V5;
 
    case bfd_mach_arm_5T:      ARM_ARCH_V5T;
 
    case bfd_mach_arm_5TE:     ARM_ARCH_V5TE;
 
    case bfd_mach_arm_XScale:  ARM_ARCH_XSCALE;
 
    case bfd_mach_arm_ep9312:  ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
 
    case bfd_mach_arm_iWMMXt:  ARM_ARCH_IWMMXT;
 
    case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
 
      /* If the machine type is unknown allow all
 
         architecture types and all extensions.  */
 
    case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
 
    default:
 
      abort ();
 
    }
 
}
 
 
 
 
/* NOTE: There are no checks in these routines that
/* NOTE: There are no checks in these routines that
   the relevant number of data bytes exist.  */
   the relevant number of data bytes exist.  */
 
 
static int
static int
print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
Line 3972... Line 4216...
  unsigned char b[4];
  unsigned char b[4];
  long          given;
  long          given;
  int           status;
  int           status;
  int           is_thumb = FALSE;
  int           is_thumb = FALSE;
  int           is_data = FALSE;
  int           is_data = FALSE;
 
  int           little_code;
  unsigned int  size = 4;
  unsigned int  size = 4;
  void          (*printer) (bfd_vma, struct disassemble_info *, long);
  void          (*printer) (bfd_vma, struct disassemble_info *, long);
  bfd_boolean   found = FALSE;
  bfd_boolean   found = FALSE;
 
 
  if (info->disassembler_options)
  if (info->disassembler_options)
Line 3984... Line 4229...
 
 
      /* To avoid repeated parsing of these options, we remove them here.  */
      /* To avoid repeated parsing of these options, we remove them here.  */
      info->disassembler_options = NULL;
      info->disassembler_options = NULL;
    }
    }
 
 
 
  /* PR 10288: Control which instructions will be disassembled.  */
 
  if (info->private_data == NULL)
 
    {
 
      static arm_feature_set features;
 
 
 
      if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
 
        /* If the user did not use the -m command line switch then default to
 
           disassembling all types of ARM instruction.
 
 
 
           The info->mach value has to be ignored as this will be based on
 
           the default archictecture for the target and/or hints in the notes
 
           section, but it will never be greater than the current largest arm
 
           machine value (iWMMXt2), which is only equivalent to the V5TE
 
           architecture.  ARM architectures have advanced beyond the machine
 
           value encoding, and these newer architectures would be ignored if
 
           the machine value was used.
 
 
 
           Ie the -m switch is used to restrict which instructions will be
 
           disassembled.  If it is necessary to use the -m switch to tell
 
           objdump that an ARM binary is being disassembled, eg because the
 
           input is a raw binary file, but it is also desired to disassemble
 
           all ARM instructions then use "-marm".  This will select the
 
           "unknown" arm architecture which is compatible with any ARM
 
           instruction.  */
 
          info->mach = bfd_mach_arm_unknown;
 
 
 
      /* Compute the architecture bitmask from the machine number.
 
         Note: This assumes that the machine number will not change
 
         during disassembly....  */
 
      select_arm_features (info->mach, & features);
 
 
 
      info->private_data = & features;
 
    }
 
 
 
  /* Decide if our code is going to be little-endian, despite what the
 
     function argument might say.  */
 
  little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
 
 
  /* First check the full symtab for a mapping symbol, even if there
  /* First check the full symtab for a mapping symbol, even if there
     are no usable non-mapping symbols for this address.  */
     are no usable non-mapping symbols for this address.  */
  if (info->symtab != NULL
  if (info->symtab_size != 0
      && * info->symtab
 
      && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
      && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
    {
    {
      bfd_vma addr;
      bfd_vma addr;
      int n;
      int n;
      int last_sym = -1;
      int last_sym = -1;
Line 4030... Line 4312...
 
 
          /* No mapping symbol found at this address.  Look backwards
          /* No mapping symbol found at this address.  Look backwards
             for a preceeding one.  */
             for a preceeding one.  */
          for (; n >= 0; n--)
          for (; n >= 0; n--)
            {
            {
              if (get_sym_code_type (info, n, &type))
              if ((info->section == NULL
 
                   || info->section == info->symtab[n]->section)
 
                  && get_sym_code_type (info, n, &type))
                {
                {
                  last_sym = n;
                  last_sym = n;
                  found = TRUE;
                  found = TRUE;
                  break;
                  break;
                }
                }
Line 4100... Line 4384...
    }
    }
 
 
  if (force_thumb)
  if (force_thumb)
    is_thumb = TRUE;
    is_thumb = TRUE;
 
 
 
  if (is_data)
  info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
  info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
 
  else
 
    info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
 
 
  info->bytes_per_line = 4;
  info->bytes_per_line = 4;
 
 
  if (is_data)
  /* PR 10263: Disassemble data if requested to do so by the user.  */
 
  if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
    {
    {
      int i;
      int i;
 
 
      /* size was already set above.  */
      /* Size was already set above.  */
      info->bytes_per_chunk = size;
      info->bytes_per_chunk = size;
      printer = print_insn_data;
      printer = print_insn_data;
 
 
      status = info->read_memory_func (pc, (bfd_byte *)b, size, info);
      status = info->read_memory_func (pc, (bfd_byte *)b, size, info);
      given = 0;
      given = 0;
Line 4129... Line 4418...
      printer = print_insn_arm;
      printer = print_insn_arm;
      info->bytes_per_chunk = 4;
      info->bytes_per_chunk = 4;
      size = 4;
      size = 4;
 
 
      status = info->read_memory_func (pc, (bfd_byte *)b, 4, info);
      status = info->read_memory_func (pc, (bfd_byte *)b, 4, info);
      if (little)
      if (little_code)
        given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
        given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
      else
      else
        given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
        given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
    }
    }
  else
  else
Line 4145... Line 4434...
      printer = print_insn_thumb16;
      printer = print_insn_thumb16;
      info->bytes_per_chunk = 2;
      info->bytes_per_chunk = 2;
      size = 2;
      size = 2;
 
 
      status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
      status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
      if (little)
      if (little_code)
        given = (b[0]) | (b[1] << 8);
        given = (b[0]) | (b[1] << 8);
      else
      else
        given = (b[1]) | (b[0] << 8);
        given = (b[1]) | (b[0] << 8);
 
 
      if (!status)
      if (!status)
Line 4159... Line 4448...
          if ((given & 0xF800) == 0xF800
          if ((given & 0xF800) == 0xF800
              || (given & 0xF800) == 0xF000
              || (given & 0xF800) == 0xF000
              || (given & 0xF800) == 0xE800)
              || (given & 0xF800) == 0xE800)
            {
            {
              status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info);
              status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info);
              if (little)
              if (little_code)
                given = (b[0]) | (b[1] << 8) | (given << 16);
                given = (b[0]) | (b[1] << 8) | (given << 16);
              else
              else
                given = (b[1]) | (b[0] << 8) | (given << 16);
                given = (b[1]) | (b[0] << 8) | (given << 16);
 
 
              printer = print_insn_thumb32;
              printer = print_insn_thumb32;
              size = 4;
              size = 4;
            }
            }
        }
        }
 
 
      if (ifthen_address != pc)
      if (ifthen_address != pc)
        find_ifthen_state(pc, info, little);
        find_ifthen_state (pc, info, little_code);
 
 
      if (ifthen_state)
      if (ifthen_state)
        {
        {
          if ((ifthen_state & 0xf) == 0x8)
          if ((ifthen_state & 0xf) == 0x8)
            ifthen_next_state = 0;
            ifthen_next_state = 0;
Line 4208... Line 4497...
}
}
 
 
int
int
print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
{
{
 
  /* Detect BE8-ness and record it in the disassembler info.  */
 
  if (info->flavour == bfd_target_elf_flavour
 
      && info->section != NULL
 
      && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
 
    info->endian_code = BFD_ENDIAN_LITTLE;
 
 
  return print_insn (pc, info, FALSE);
  return print_insn (pc, info, FALSE);
}
}
 
 
int
int
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.