| Line 1... |
Line 1... |
/* Disassemble ADI Blackfin Instructions.
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/* Disassemble ADI Blackfin Instructions.
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Copyright 2005, 2007 Free Software Foundation, Inc.
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Copyright 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
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This file is part of libopcodes.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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| Line 49... |
Line 49... |
#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
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#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
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#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
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#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
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#include "dis-asm.h"
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#include "dis-asm.h"
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typedef unsigned int bu32;
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typedef enum
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typedef enum
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{
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{
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c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
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c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
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c_imm4, c_uimm4s4, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_uimm5, c_imm6,
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c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
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c_imm7, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
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c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
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c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
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c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
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c_uimm16, c_pcrel24,
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c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
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} const_forms_t;
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} const_forms_t;
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static struct
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static struct
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{
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{
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char *name;
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char *name;
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| Line 69... |
Line 71... |
char pcrel;
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char pcrel;
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char scale;
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char scale;
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char offset;
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char offset;
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char negative;
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char negative;
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char positive;
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char positive;
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char decimal;
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char leading;
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char exact;
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} constant_formats[] =
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} constant_formats[] =
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{
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{
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{ "0", 0, 0, 1, 0, 0, 0, 0, 0},
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{ "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "1", 0, 0, 1, 0, 0, 0, 0, 0},
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{ "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "4", 0, 0, 1, 0, 0, 0, 0, 0},
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{ "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "2", 0, 0, 1, 0, 0, 0, 0, 0},
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{ "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "uimm2", 2, 0, 0, 0, 0, 0, 0, 0},
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{ "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "uimm3", 3, 0, 0, 0, 0, 0, 0, 0},
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{ "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "imm3", 3, 0, 1, 0, 0, 0, 0, 0},
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{ "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0},
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{ "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
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{ "imm4", 4, 0, 1, 0, 0, 0, 0, 0},
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{ "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1},
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{ "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
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{ "uimm4", 4, 0, 0, 0, 0, 0, 0, 0},
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{ "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
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{ "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1},
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{ "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0},
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{ "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
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{ "imm5", 5, 0, 1, 0, 0, 0, 0, 0},
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{ "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
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{ "uimm5", 5, 0, 0, 0, 0, 0, 0, 0},
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{ "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "imm6", 6, 0, 1, 0, 0, 0, 0, 0},
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{ "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
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{ "imm7", 7, 0, 1, 0, 0, 0, 0, 0},
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{ "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "imm8", 8, 0, 1, 0, 0, 0, 0, 0},
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{ "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "uimm8", 8, 0, 0, 0, 0, 0, 0, 0},
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{ "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0},
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{ "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
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{ "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0},
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{ "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0},
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{ "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0},
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{ "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
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{ "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0},
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{ "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
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{ "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0},
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{ "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
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{ "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0},
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{ "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
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{ "luimm16", 16, 1, 0, 0, 0, 0, 0, 0},
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{ "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
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{ "imm16", 16, 0, 1, 0, 0, 0, 0, 0},
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{ "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
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{ "huimm16", 16, 1, 0, 0, 0, 0, 0, 0},
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{ "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
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{ "rimm16", 16, 1, 1, 0, 0, 0, 0, 0},
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{ "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0},
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{ "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0},
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{ "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
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{ "uimm16", 16, 0, 0, 0, 0, 0, 0, 0},
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{ "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0}
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{ "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
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{ "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
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{ "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
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{ "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
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{ "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
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{ "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{ "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
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};
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};
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int _print_insn_bfin (bfd_vma pc, disassemble_info * outf);
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static char comment = 0;
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int print_insn_bfin (bfd_vma pc, disassemble_info * outf);
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static char parallel = 0;
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static char *
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static char *
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fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf)
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fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf)
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{
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{
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static char buf[60];
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static char buf[60];
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| Line 122... |
Line 136... |
bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
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bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
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: x) + constant_formats[cf].offset) << constant_formats[cf].scale);
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: x) + constant_formats[cf].offset) << constant_formats[cf].scale);
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if (constant_formats[cf].pcrel)
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if (constant_formats[cf].pcrel)
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ea += pc;
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ea += pc;
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if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
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{
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outf->print_address_func (ea, outf);
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outf->print_address_func (ea, outf);
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return "";
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return "";
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}
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}
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else
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{
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sprintf (buf, "%lx", (unsigned long) x);
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return buf;
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}
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}
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/* Negative constants have an implied sign bit. */
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/* Negative constants have an implied sign bit. */
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if (constant_formats[cf].negative)
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if (constant_formats[cf].negative)
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{
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{
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int nb = constant_formats[cf].nbits + 1;
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int nb = constant_formats[cf].nbits + 1;
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| Line 143... |
Line 165... |
x += constant_formats[cf].offset;
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x += constant_formats[cf].offset;
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if (constant_formats[cf].scale)
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if (constant_formats[cf].scale)
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x <<= constant_formats[cf].scale;
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x <<= constant_formats[cf].scale;
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if (constant_formats[cf].decimal)
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{
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if (constant_formats[cf].leading)
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{
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char ps[10];
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sprintf (ps, "%%%ii", constant_formats[cf].leading);
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sprintf (buf, ps, x);
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}
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else
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sprintf (buf, "%li", x);
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}
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else
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{
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if (constant_formats[cf].issigned && x < 0)
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if (constant_formats[cf].issigned && x < 0)
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sprintf (buf, "%ld", x);
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sprintf (buf, "-0x%x", abs (x));
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else
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else
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sprintf (buf, "0x%lx", x);
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sprintf (buf, "0x%lx", (unsigned long) x);
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}
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return buf;
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return buf;
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}
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}
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static bu32
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fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
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{
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if (0 && constant_formats[cf].reloc)
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{
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bu32 ea = (((constant_formats[cf].pcrel
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? SIGNEXTEND (x, constant_formats[cf].nbits)
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: x) + constant_formats[cf].offset)
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<< constant_formats[cf].scale);
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if (constant_formats[cf].pcrel)
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ea += pc;
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return ea;
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}
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/* Negative constants have an implied sign bit. */
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if (constant_formats[cf].negative)
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{
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int nb = constant_formats[cf].nbits + 1;
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x = x | (1 << constant_formats[cf].nbits);
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x = SIGNEXTEND (x, nb);
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}
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else if (constant_formats[cf].issigned)
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x = SIGNEXTEND (x, constant_formats[cf].nbits);
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x += constant_formats[cf].offset;
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x <<= constant_formats[cf].scale;
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return x;
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}
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enum machine_registers
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enum machine_registers
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{
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{
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REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
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REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
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REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
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REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
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REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
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REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
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| Line 191... |
Line 258... |
{
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{
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"R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
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"R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
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"R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
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"R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
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"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
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"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
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"R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
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"R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
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"P4", "P5", "SP", "FP", "A0.x", "A1.x", "A0.w", "A1.w",
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"P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
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"A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
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"A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
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"M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
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"M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
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"L2", "L3",
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"L2", "L3",
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"AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
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"AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
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"AQ", "V", "VS",
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"AQ", "V", "VS",
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| Line 245... |
Line 312... |
{
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{
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REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
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REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
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};
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};
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#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
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#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
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#define dregs_pair(x) REGNAME (decode_dregs_pair[(x) & 7])
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|
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/* P(0..5) SP FP. */
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/* P(0..5) SP FP. */
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static enum machine_registers decode_pregs[] =
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static enum machine_registers decode_pregs[] =
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{
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{
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REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
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REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
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| Line 337... |
Line 403... |
REG_AV0, REG_AV0S, REG_AV1, REG_AV1S, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
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REG_AV0, REG_AV0S, REG_AV1, REG_AV1S, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
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REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
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REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
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};
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};
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|
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#define statbits(x) REGNAME (decode_statbits[(x) & 31])
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#define statbits(x) REGNAME (decode_statbits[(x) & 31])
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#define ignore_bits(x) REGNAME (decode_ignore_bits[(x) & 7])
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#define ccstat(x) REGNAME (decode_ccstat[(x) & 0])
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|
|
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/* LC0 LC1. */
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/* LC0 LC1. */
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static enum machine_registers decode_counters[] =
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static enum machine_registers decode_counters[] =
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{
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{
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REG_LC0, REG_LC1,
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REG_LC0, REG_LC1,
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| Line 360... |
Line 424... |
REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
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REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
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REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
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REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
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REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
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REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
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REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
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REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
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REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
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REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
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REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_LASTREG,
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REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
|
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REG_LASTREG,
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};
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};
|
|
|
|
#define IS_DREG(g,r) ((g) == 0)
|
|
#define IS_PREG(g,r) ((g) == 1)
|
|
#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
|
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#define IS_GENREG(g,r) ((g) == 0 || (g) == 1 || IS_AREG (g, r))
|
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#define IS_DAGREG(g,r) ((g) == 2 || (g) == 3)
|
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#define IS_SYSREG(g,r) \
|
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(((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
|
|
|
#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
|
#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
|
#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
|
#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
|
|
#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
|
#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
|
#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
|
#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
|
#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
|
#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
|
#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
|
#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
|
#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
|
#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
|
#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
|
#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
|
#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
|
#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
|
#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
|
#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
|
#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
|
#define imm16(x) fmtconst (c_imm16, x, 0, outf)
|
#define imm16(x) fmtconst (c_imm16, x, 0, outf)
|
|
#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
|
#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
|
#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
|
#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
|
#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
|
#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
|
#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
|
#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
|
#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
|
#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
|
#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
|
#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
|
#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
|
#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
|
#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
|
#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
|
#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
|
#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
|
#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
|
#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
|
#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
|
|
#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
|
#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
|
#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
|
#define imm3(x) fmtconst (c_imm3, x, 0, outf)
|
#define imm3(x) fmtconst (c_imm3, x, 0, outf)
|
#define imm4(x) fmtconst (c_imm4, x, 0, outf)
|
#define imm4(x) fmtconst (c_imm4, x, 0, outf)
|
#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
|
#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
|
#define imm5(x) fmtconst (c_imm5, x, 0, outf)
|
#define imm5(x) fmtconst (c_imm5, x, 0, outf)
|
|
#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
|
#define imm6(x) fmtconst (c_imm6, x, 0, outf)
|
#define imm6(x) fmtconst (c_imm6, x, 0, outf)
|
#define imm7(x) fmtconst (c_imm7, x, 0, outf)
|
#define imm7(x) fmtconst (c_imm7, x, 0, outf)
|
|
#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
|
#define imm8(x) fmtconst (c_imm8, x, 0, outf)
|
#define imm8(x) fmtconst (c_imm8, x, 0, outf)
|
#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
|
#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
|
#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
|
#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
|
|
#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
|
|
#define imm32(x) fmtconst (c_imm32, x, 0, outf)
|
|
#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
|
|
#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
|
|
#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
|
|
#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
|
|
#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
|
|
|
/* (arch.pm)arch_disassembler_functions. */
|
/* (arch.pm)arch_disassembler_functions. */
|
#ifndef OUTS
|
#ifndef OUTS
|
#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, txt) :0) :0)
|
#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
|
#endif
|
#endif
|
|
|
static void
|
static void
|
amod0 (int s0, int x0, disassemble_info *outf)
|
amod0 (int s0, int x0, disassemble_info *outf)
|
{
|
{
|
| Line 495... |
Line 580... |
{
|
{
|
char *a;
|
char *a;
|
char *sop = "<unknown op>";
|
char *sop = "<unknown op>";
|
|
|
if (which)
|
if (which)
|
a = "a1";
|
a = "A1";
|
else
|
else
|
a = "a0";
|
a = "A0";
|
|
|
if (op == 3)
|
if (op == 3)
|
{
|
{
|
OUTS (outf, a);
|
OUTS (outf, a);
|
return 0;
|
return 0;
|
| Line 514... |
Line 599... |
case 2: sop = "-="; break;
|
case 2: sop = "-="; break;
|
default: break;
|
default: break;
|
}
|
}
|
|
|
OUTS (outf, a);
|
OUTS (outf, a);
|
OUTS (outf, " ");
|
|
OUTS (outf, sop);
|
OUTS (outf, sop);
|
OUTS (outf, " ");
|
|
decode_multfunc (h0, h1, src0, src1, outf);
|
decode_multfunc (h0, h1, src0, src1, outf);
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
| Line 563... |
Line 646... |
abort ();
|
abort ();
|
|
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
|
|
|
struct saved_state
|
|
{
|
|
bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
|
|
bu32 a0x, a0w, a1x, a1w;
|
|
bu32 lt[2], lc[2], lb[2];
|
|
int ac0, ac0_copy, ac1, an, aq;
|
|
int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
|
|
int rnd_mod;
|
|
int v_internal;
|
|
bu32 pc, rets;
|
|
|
|
int ticks;
|
|
int insts;
|
|
|
|
int exception;
|
|
|
|
int end_of_registers;
|
|
|
|
int msize;
|
|
unsigned char *memory;
|
|
unsigned long bfd_mach;
|
|
} saved_state;
|
|
|
|
#define DREG(x) (saved_state.dpregs[x])
|
|
#define GREG(x,i) DPREG ((x) | (i << 3))
|
|
#define DPREG(x) (saved_state.dpregs[x])
|
|
#define DREG(x) (saved_state.dpregs[x])
|
|
#define PREG(x) (saved_state.dpregs[x + 8])
|
|
#define SPREG PREG (6)
|
|
#define FPREG PREG (7)
|
|
#define IREG(x) (saved_state.iregs[x])
|
|
#define MREG(x) (saved_state.mregs[x])
|
|
#define BREG(x) (saved_state.bregs[x])
|
|
#define LREG(x) (saved_state.lregs[x])
|
|
#define A0XREG (saved_state.a0x)
|
|
#define A0WREG (saved_state.a0w)
|
|
#define A1XREG (saved_state.a1x)
|
|
#define A1WREG (saved_state.a1w)
|
|
#define CCREG (saved_state.cc)
|
|
#define LC0REG (saved_state.lc[0])
|
|
#define LT0REG (saved_state.lt[0])
|
|
#define LB0REG (saved_state.lb[0])
|
|
#define LC1REG (saved_state.lc[1])
|
|
#define LT1REG (saved_state.lt[1])
|
|
#define LB1REG (saved_state.lb[1])
|
|
#define RETSREG (saved_state.rets)
|
|
#define PCREG (saved_state.pc)
|
|
|
|
static bu32 *
|
|
get_allreg (int grp, int reg)
|
|
{
|
|
int fullreg = (grp << 3) | reg;
|
|
/* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
|
|
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
|
|
REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
|
|
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
|
|
REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
|
|
, , , , , , , ,
|
|
REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
|
|
REG_CYCLES2,
|
|
REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
|
|
REG_LASTREG */
|
|
switch (fullreg >> 2)
|
|
{
|
|
case 0: case 1: return &DREG (reg); break;
|
|
case 2: case 3: return &PREG (reg); break;
|
|
case 4: return &IREG (reg & 3); break;
|
|
case 5: return &MREG (reg & 3); break;
|
|
case 6: return &BREG (reg & 3); break;
|
|
case 7: return &LREG (reg & 3); break;
|
|
default:
|
|
switch (fullreg)
|
|
{
|
|
case 32: return &saved_state.a0x;
|
|
case 33: return &saved_state.a0w;
|
|
case 34: return &saved_state.a1x;
|
|
case 35: return &saved_state.a1w;
|
|
case 39: return &saved_state.rets;
|
|
case 48: return &LC0REG;
|
|
case 49: return <0REG;
|
|
case 50: return &LB0REG;
|
|
case 51: return &LC1REG;
|
|
case 52: return <1REG;
|
|
case 53: return &LB1REG;
|
|
}
|
|
return 0;
|
|
}
|
|
}
|
|
|
static int
|
static int
|
decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
|
decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
|
{
|
{
|
/* ProgCtrl
|
/* ProgCtrl
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
|
| Line 750... |
Line 922... |
int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
|
int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
|
int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
|
int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
|
int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
|
int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
|
int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
|
int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
|
int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
|
int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
|
char ps[5], ds[5];
|
|
|
|
sprintf (ps, "%d", pr);
|
|
sprintf (ds, "%d", dr);
|
|
|
|
if (W == 1 && d == 1 && p == 1)
|
if (W == 1 && d == 1 && p == 1)
|
{
|
{
|
OUTS (outf, "[--SP] = (R7:");
|
OUTS (outf, "[--SP] = (R7:");
|
OUTS (outf, ds);
|
OUTS (outf, imm5d (dr));
|
OUTS (outf, ", P5:");
|
OUTS (outf, ", P5:");
|
OUTS (outf, ps);
|
OUTS (outf, imm5d (pr));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
else if (W == 1 && d == 1 && p == 0)
|
else if (W == 1 && d == 1 && p == 0)
|
{
|
{
|
OUTS (outf, "[--SP] = (R7:");
|
OUTS (outf, "[--SP] = (R7:");
|
OUTS (outf, ds);
|
OUTS (outf, imm5d (dr));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
else if (W == 1 && d == 0 && p == 1)
|
else if (W == 1 && d == 0 && p == 1)
|
{
|
{
|
OUTS (outf, "[--SP] = (P5:");
|
OUTS (outf, "[--SP] = (P5:");
|
OUTS (outf, ps);
|
OUTS (outf, imm5d (pr));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
else if (W == 0 && d == 1 && p == 1)
|
else if (W == 0 && d == 1 && p == 1)
|
{
|
{
|
OUTS (outf, "(R7:");
|
OUTS (outf, "(R7:");
|
OUTS (outf, ds);
|
OUTS (outf, imm5d (dr));
|
OUTS (outf, ", P5:");
|
OUTS (outf, ", P5:");
|
OUTS (outf, ps);
|
OUTS (outf, imm5d (pr));
|
OUTS (outf, ") = [SP++]");
|
OUTS (outf, ") = [SP++]");
|
}
|
}
|
else if (W == 0 && d == 1 && p == 0)
|
else if (W == 0 && d == 1 && p == 0)
|
{
|
{
|
OUTS (outf, "(R7:");
|
OUTS (outf, "(R7:");
|
OUTS (outf, ds);
|
OUTS (outf, imm5d (dr));
|
OUTS (outf, ") = [SP++]");
|
OUTS (outf, ") = [SP++]");
|
}
|
}
|
else if (W == 0 && d == 0 && p == 1)
|
else if (W == 0 && d == 0 && p == 1)
|
{
|
{
|
OUTS (outf, "(P5:");
|
OUTS (outf, "(P5:");
|
OUTS (outf, ps);
|
OUTS (outf, imm5d (pr));
|
OUTS (outf, ") = [SP++]");
|
OUTS (outf, ") = [SP++]");
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
return 2;
|
return 2;
|
| Line 1105... |
Line 1273... |
int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
|
int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
|
int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
|
int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
|
|
|
if (T == 1 && B == 1)
|
if (T == 1 && B == 1)
|
{
|
{
|
OUTS (outf, "IF CC JUMP ");
|
OUTS (outf, "IF CC JUMP 0x");
|
OUTS (outf, pcrel10 (offset));
|
OUTS (outf, pcrel10 (offset));
|
OUTS (outf, "(BP)");
|
OUTS (outf, "(BP)");
|
}
|
}
|
else if (T == 0 && B == 1)
|
else if (T == 0 && B == 1)
|
{
|
{
|
OUTS (outf, "IF ! CC JUMP ");
|
OUTS (outf, "IF !CC JUMP 0x");
|
OUTS (outf, pcrel10 (offset));
|
OUTS (outf, pcrel10 (offset));
|
OUTS (outf, "(BP)");
|
OUTS (outf, "(BP)");
|
}
|
}
|
else if (T == 1)
|
else if (T == 1)
|
{
|
{
|
OUTS (outf, "IF CC JUMP ");
|
OUTS (outf, "IF CC JUMP 0x");
|
OUTS (outf, pcrel10 (offset));
|
OUTS (outf, pcrel10 (offset));
|
}
|
}
|
else if (T == 0)
|
else if (T == 0)
|
{
|
{
|
OUTS (outf, "IF ! CC JUMP ");
|
OUTS (outf, "IF !CC JUMP 0x");
|
OUTS (outf, pcrel10 (offset));
|
OUTS (outf, pcrel10 (offset));
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
|
|
| Line 1140... |
Line 1308... |
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
|
| 0 | 0 | 1 | 0 |.offset........................................|
|
| 0 | 0 | 1 | 0 |.offset........................................|
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
|
int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
|
int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
|
|
|
OUTS (outf, "JUMP.S ");
|
OUTS (outf, "JUMP.S 0x");
|
OUTS (outf, pcrel12 (offset));
|
OUTS (outf, pcrel12 (offset));
|
return 2;
|
return 2;
|
}
|
}
|
|
|
static int
|
static int
|
| Line 1157... |
Line 1325... |
int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
|
int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
|
int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
|
int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
|
int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
|
int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
|
int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
|
int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
|
|
|
|
if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src))
|
|
|| (IS_GENREG (gd, dst) && IS_DAGREG (gs, src))
|
|
|| (IS_DAGREG (gd, dst) && IS_GENREG (gs, src))
|
|
|| (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src))
|
|
|| (IS_GENREG (gd, dst) && gs == 7 && src == 0)
|
|
|| (gd == 7 && dst == 0 && IS_GENREG (gs, src))
|
|
|| (IS_DREG (gd, dst) && IS_SYSREG (gs, src))
|
|
|| (IS_PREG (gd, dst) && IS_SYSREG (gs, src))
|
|
|| (IS_SYSREG (gd, dst) && IS_DREG (gs, src))
|
|
|| (IS_SYSREG (gd, dst) && IS_PREG (gs, src))
|
|
|| (IS_SYSREG (gd, dst) && gs == 7 && src == 0)))
|
|
return 0;
|
|
|
OUTS (outf, allregs (dst, gd));
|
OUTS (outf, allregs (dst, gd));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, allregs (src, gs));
|
OUTS (outf, allregs (src, gs));
|
return 2;
|
return 2;
|
}
|
}
|
| Line 1205... |
Line 1386... |
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, "=(");
|
OUTS (outf, "=(");
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs (src));
|
OUTS (outf, dregs (src));
|
OUTS (outf, ")<<1");
|
OUTS (outf, ") << 0x1");
|
}
|
}
|
else if (opc == 5)
|
else if (opc == 5)
|
{
|
{
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, "=(");
|
OUTS (outf, "=(");
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs (src));
|
OUTS (outf, dregs (src));
|
OUTS (outf, ")<<2");
|
OUTS (outf, ") << 0x2");
|
}
|
}
|
else if (opc == 8)
|
else if (opc == 8)
|
{
|
{
|
OUTS (outf, "DIVQ(");
|
OUTS (outf, "DIVQ(");
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
| Line 1300... |
Line 1481... |
else if (opc == 1)
|
else if (opc == 1)
|
{
|
{
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, pregs (src));
|
OUTS (outf, pregs (src));
|
OUTS (outf, "<<2");
|
OUTS (outf, " << 0x2");
|
}
|
}
|
else if (opc == 3)
|
else if (opc == 3)
|
{
|
{
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, pregs (src));
|
OUTS (outf, pregs (src));
|
OUTS (outf, ">>2");
|
OUTS (outf, " >> 0x2");
|
}
|
}
|
else if (opc == 4)
|
else if (opc == 4)
|
{
|
{
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, pregs (src));
|
OUTS (outf, pregs (src));
|
OUTS (outf, ">>1");
|
OUTS (outf, " >> 0x1");
|
}
|
}
|
else if (opc == 5)
|
else if (opc == 5)
|
{
|
{
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "+=");
|
OUTS (outf, "+=");
|
| Line 1330... |
Line 1511... |
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "=(");
|
OUTS (outf, "=(");
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, pregs (src));
|
OUTS (outf, pregs (src));
|
OUTS (outf, ")<<1");
|
OUTS (outf, ") << 0x1");
|
}
|
}
|
else if (opc == 7)
|
else if (opc == 7)
|
{
|
{
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "=(");
|
OUTS (outf, "=(");
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, pregs (src));
|
OUTS (outf, pregs (src));
|
OUTS (outf, ")<<2");
|
OUTS (outf, ") << 0x2");
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
|
|
return 2;
|
return 2;
|
| Line 1364... |
Line 1545... |
{
|
{
|
OUTS (outf, "CC = ! BITTST (");
|
OUTS (outf, "CC = ! BITTST (");
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, ")");
|
OUTS (outf, ");\t\t/* bit");
|
|
OUTS (outf, imm7d (src));
|
|
OUTS (outf, " */");
|
|
comment = 1;
|
}
|
}
|
else if (opc == 1)
|
else if (opc == 1)
|
{
|
{
|
OUTS (outf, "CC = BITTST (");
|
OUTS (outf, "CC = BITTST (");
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, ")");
|
OUTS (outf, ");\t\t/* bit");
|
|
OUTS (outf, imm7d (src));
|
|
OUTS (outf, " */");
|
|
comment = 1;
|
}
|
}
|
else if (opc == 2)
|
else if (opc == 2)
|
{
|
{
|
OUTS (outf, "BITSET (");
|
OUTS (outf, "BITSET (");
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, ")");
|
OUTS (outf, ");\t\t/* bit");
|
|
OUTS (outf, imm7d (src));
|
|
OUTS (outf, " */");
|
|
comment = 1;
|
}
|
}
|
else if (opc == 3)
|
else if (opc == 3)
|
{
|
{
|
OUTS (outf, "BITTGL (");
|
OUTS (outf, "BITTGL (");
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, ")");
|
OUTS (outf, ");\t\t/* bit");
|
|
OUTS (outf, imm7d (src));
|
|
OUTS (outf, " */");
|
|
comment = 1;
|
}
|
}
|
else if (opc == 4)
|
else if (opc == 4)
|
{
|
{
|
OUTS (outf, "BITCLR (");
|
OUTS (outf, "BITCLR (");
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, uimm5 (src));
|
OUTS (outf, ")");
|
OUTS (outf, ");\t\t/* bit");
|
|
OUTS (outf, imm7d (src));
|
|
OUTS (outf, " */");
|
|
comment = 1;
|
}
|
}
|
else if (opc == 5)
|
else if (opc == 5)
|
{
|
{
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, ">>>=");
|
OUTS (outf, ">>>=");
|
| Line 1439... |
Line 1635... |
if (opc == 5 && src1 == src0)
|
if (opc == 5 && src1 == src0)
|
{
|
{
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, pregs (src0));
|
OUTS (outf, pregs (src0));
|
OUTS (outf, "<<1");
|
OUTS (outf, " << 0x1");
|
}
|
}
|
else if (opc == 1)
|
else if (opc == 1)
|
{
|
{
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
| Line 1488... |
Line 1684... |
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, pregs (src0));
|
OUTS (outf, pregs (src0));
|
OUTS (outf, "+(");
|
OUTS (outf, "+(");
|
OUTS (outf, pregs (src1));
|
OUTS (outf, pregs (src1));
|
OUTS (outf, "<<1)");
|
OUTS (outf, " << 0x1)");
|
}
|
}
|
else if (opc == 7)
|
else if (opc == 7)
|
{
|
{
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, pregs (src0));
|
OUTS (outf, pregs (src0));
|
OUTS (outf, "+(");
|
OUTS (outf, "+(");
|
OUTS (outf, pregs (src1));
|
OUTS (outf, pregs (src1));
|
OUTS (outf, "<<2)");
|
OUTS (outf, " << 0x2)");
|
}
|
}
|
else if (opc == 0)
|
else if (opc == 0)
|
{
|
{
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
| Line 1524... |
Line 1720... |
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
|
int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
|
int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
|
int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
|
int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
|
int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
|
int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
|
|
|
|
bu32 *pval = get_allreg (0, dst);
|
|
|
|
/* Since we don't have 32-bit immediate loads, we allow the disassembler
|
|
to combine them, so it prints out the right values.
|
|
Here we keep track of the registers. */
|
|
if (op == 0)
|
|
{
|
|
*pval = imm7_val (src);
|
|
if (src & 0x40)
|
|
*pval |= 0xFFFFFF80;
|
|
else
|
|
*pval &= 0x7F;
|
|
}
|
|
|
if (op == 0)
|
if (op == 0)
|
{
|
{
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, imm7 (src));
|
OUTS (outf, imm7 (src));
|
OUTS (outf, "(x)");
|
OUTS (outf, " (X);\t\t/*\t\t");
|
|
OUTS (outf, dregs (dst));
|
|
OUTS (outf, "=");
|
|
OUTS (outf, uimm32 (*pval));
|
|
OUTS (outf, "(");
|
|
OUTS (outf, imm32 (*pval));
|
|
OUTS (outf, ") */");
|
|
comment = 1;
|
}
|
}
|
else if (op == 1)
|
else if (op == 1)
|
{
|
{
|
OUTS (outf, dregs (dst));
|
OUTS (outf, dregs (dst));
|
OUTS (outf, "+=");
|
OUTS (outf, "+=");
|
OUTS (outf, imm7 (src));
|
OUTS (outf, imm7 (src));
|
|
OUTS (outf, ";\t\t/* (");
|
|
OUTS (outf, imm7d (src));
|
|
OUTS (outf, ") */");
|
|
comment = 1;
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
|
|
return 2;
|
return 2;
|
| Line 1554... |
Line 1775... |
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
|
int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
|
int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
|
int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
|
int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
|
int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
|
int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
|
|
|
|
bu32 *pval = get_allreg (1, dst);
|
|
|
|
if (op == 0)
|
|
{
|
|
*pval = imm7_val (src);
|
|
if (src & 0x40)
|
|
*pval |= 0xFFFFFF80;
|
|
else
|
|
*pval &= 0x7F;
|
|
}
|
|
|
if (op == 0)
|
if (op == 0)
|
{
|
{
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, imm7 (src));
|
OUTS (outf, imm7 (src));
|
|
OUTS (outf, " (X);\t\t/*\t\t");
|
|
OUTS (outf, pregs (dst));
|
|
OUTS (outf, "=");
|
|
OUTS (outf, uimm32 (*pval));
|
|
OUTS (outf, "(");
|
|
OUTS (outf, imm32 (*pval));
|
|
OUTS (outf, ") */");
|
|
comment = 1;
|
}
|
}
|
else if (op == 1)
|
else if (op == 1)
|
{
|
{
|
OUTS (outf, pregs (dst));
|
OUTS (outf, pregs (dst));
|
OUTS (outf, "+=");
|
OUTS (outf, "+=");
|
OUTS (outf, imm7 (src));
|
OUTS (outf, imm7 (src));
|
|
OUTS (outf, ";\t\t/* (");
|
|
OUTS (outf, imm7d (src));
|
|
OUTS (outf, ") */");
|
|
comment = 1;
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
|
|
return 2;
|
return 2;
|
| Line 1741... |
Line 1985... |
int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
|
int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
|
|
|
if (op == 0)
|
if (op == 0)
|
{
|
{
|
OUTS (outf, iregs (i));
|
OUTS (outf, iregs (i));
|
OUTS (outf, "+=2");
|
OUTS (outf, " += 0x2");
|
}
|
}
|
else if (op == 1)
|
else if (op == 1)
|
{
|
{
|
OUTS (outf, iregs (i));
|
OUTS (outf, iregs (i));
|
OUTS (outf, "-=2");
|
OUTS (outf, " -= 0x2");
|
}
|
}
|
else if (op == 2)
|
else if (op == 2)
|
{
|
{
|
OUTS (outf, iregs (i));
|
OUTS (outf, iregs (i));
|
OUTS (outf, "+=4");
|
OUTS (outf, " += 0x4");
|
}
|
}
|
else if (op == 3)
|
else if (op == 3)
|
{
|
{
|
OUTS (outf, iregs (i));
|
OUTS (outf, iregs (i));
|
OUTS (outf, "-=4");
|
OUTS (outf, " -= 0x4");
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
|
|
|
if (! parallel )
|
|
{
|
|
OUTS (outf, ";\t\t/* ( ");
|
|
if (op == 0 || op == 1)
|
|
OUTS (outf, "2");
|
|
else if (op == 2 || op == 3)
|
|
OUTS (outf, "4");
|
|
OUTS (outf, ") */");
|
|
comment = 1;
|
|
}
|
|
|
return 2;
|
return 2;
|
}
|
}
|
|
|
static int
|
static int
|
decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
|
decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
|
| Line 2248... |
Line 2503... |
OUTS (outf, "]=");
|
OUTS (outf, "]=");
|
OUTS (outf, dregs (reg));
|
OUTS (outf, dregs (reg));
|
}
|
}
|
else if (W == 1 && op == 1)
|
else if (W == 1 && op == 1)
|
{
|
{
|
OUTS (outf, "W");
|
OUTS (outf, "W[");
|
OUTS (outf, "[");
|
|
OUTS (outf, pregs (ptr));
|
OUTS (outf, pregs (ptr));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, uimm4s2 (offset));
|
OUTS (outf, uimm4s2 (offset));
|
OUTS (outf, "]");
|
OUTS (outf, "] = ");
|
OUTS (outf, "=");
|
|
OUTS (outf, dregs (reg));
|
OUTS (outf, dregs (reg));
|
}
|
}
|
else if (W == 1 && op == 3)
|
else if (W == 1 && op == 3)
|
{
|
{
|
OUTS (outf, "[");
|
OUTS (outf, "[");
|
| Line 2289... |
Line 2542... |
int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
|
int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
|
|
|
if (rop == 0)
|
if (rop == 0)
|
{
|
{
|
OUTS (outf, "LSETUP");
|
OUTS (outf, "LSETUP");
|
OUTS (outf, "(");
|
OUTS (outf, "(0x");
|
OUTS (outf, pcrel4 (soffset));
|
OUTS (outf, pcrel4 (soffset));
|
OUTS (outf, ",");
|
OUTS (outf, ", 0x");
|
OUTS (outf, lppcrel10 (eoffset));
|
OUTS (outf, lppcrel10 (eoffset));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
OUTS (outf, counters (c));
|
OUTS (outf, counters (c));
|
}
|
}
|
else if (rop == 1)
|
else if (rop == 1)
|
{
|
{
|
OUTS (outf, "LSETUP");
|
OUTS (outf, "LSETUP");
|
OUTS (outf, "(");
|
OUTS (outf, "(0x");
|
OUTS (outf, pcrel4 (soffset));
|
OUTS (outf, pcrel4 (soffset));
|
OUTS (outf, ",");
|
OUTS (outf, ", 0x");
|
OUTS (outf, lppcrel10 (eoffset));
|
OUTS (outf, lppcrel10 (eoffset));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
OUTS (outf, counters (c));
|
OUTS (outf, counters (c));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, pregs (reg));
|
OUTS (outf, pregs (reg));
|
}
|
}
|
else if (rop == 3)
|
else if (rop == 3)
|
{
|
{
|
OUTS (outf, "LSETUP");
|
OUTS (outf, "LSETUP");
|
OUTS (outf, "(");
|
OUTS (outf, "(0x");
|
OUTS (outf, pcrel4 (soffset));
|
OUTS (outf, pcrel4 (soffset));
|
OUTS (outf, ",");
|
OUTS (outf, ", 0x");
|
OUTS (outf, lppcrel10 (eoffset));
|
OUTS (outf, lppcrel10 (eoffset));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
OUTS (outf, counters (c));
|
OUTS (outf, counters (c));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, pregs (reg));
|
OUTS (outf, pregs (reg));
|
OUTS (outf, ">>1");
|
OUTS (outf, " >> 0x1");
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
|
|
return 4;
|
return 4;
|
| Line 2342... |
Line 2595... |
int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
|
int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
|
int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
|
int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
|
int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
|
int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
|
int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
|
int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
|
|
|
|
bu32 *pval = get_allreg (grp, reg);
|
|
|
|
/* Since we don't have 32-bit immediate loads, we allow the disassembler
|
|
to combine them, so it prints out the right values.
|
|
Here we keep track of the registers. */
|
|
if (H == 0 && S == 1 && Z == 0)
|
|
{
|
|
/* regs = imm16 (x) */
|
|
*pval = imm16_val (hword);
|
|
if (hword & 0x8000)
|
|
*pval |= 0xFFFF0000;
|
|
else
|
|
*pval &= 0xFFFF;
|
|
}
|
|
else if (H == 0 && S == 0 && Z == 1)
|
|
{
|
|
/* regs = luimm16 (Z) */
|
|
*pval = luimm16_val (hword);
|
|
*pval &= 0xFFFF;
|
|
}
|
|
else if (H == 0 && S == 0 && Z == 0)
|
|
{
|
|
/* regs_lo = luimm16 */
|
|
*pval &= 0xFFFF0000;
|
|
*pval |= luimm16_val (hword);
|
|
}
|
|
else if (H == 1 && S == 0 && Z == 0)
|
|
{
|
|
/* regs_hi = huimm16 */
|
|
*pval &= 0xFFFF;
|
|
*pval |= luimm16_val (hword) << 16;
|
|
}
|
|
|
|
/* Here we do the disassembly */
|
if (grp == 0 && H == 0 && S == 0 && Z == 0)
|
if (grp == 0 && H == 0 && S == 0 && Z == 0)
|
{
|
{
|
OUTS (outf, dregs_lo (reg));
|
OUTS (outf, dregs_lo (reg));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, imm16 (hword));
|
OUTS (outf, uimm16 (hword));
|
}
|
}
|
else if (grp == 0 && H == 1 && S == 0 && Z == 0)
|
else if (grp == 0 && H == 1 && S == 0 && Z == 0)
|
{
|
{
|
OUTS (outf, dregs_hi (reg));
|
OUTS (outf, dregs_hi (reg));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, imm16 (hword));
|
OUTS (outf, uimm16 (hword));
|
}
|
}
|
else if (grp == 0 && H == 0 && S == 1 && Z == 0)
|
else if (grp == 0 && H == 0 && S == 1 && Z == 0)
|
{
|
{
|
OUTS (outf, dregs (reg));
|
OUTS (outf, dregs (reg));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
| Line 2372... |
Line 2659... |
}
|
}
|
else if (H == 0 && S == 0 && Z == 1)
|
else if (H == 0 && S == 0 && Z == 1)
|
{
|
{
|
OUTS (outf, regs (reg, grp));
|
OUTS (outf, regs (reg, grp));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, luimm16 (hword));
|
OUTS (outf, uimm16 (hword));
|
OUTS (outf, "(Z)");
|
OUTS (outf, "(Z)");
|
}
|
}
|
else if (H == 0 && S == 0 && Z == 0)
|
else if (H == 0 && S == 0 && Z == 0)
|
{
|
{
|
OUTS (outf, regs_lo (reg, grp));
|
OUTS (outf, regs_lo (reg, grp));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, luimm16 (hword));
|
OUTS (outf, uimm16 (hword));
|
}
|
}
|
else if (H == 1 && S == 0 && Z == 0)
|
else if (H == 1 && S == 0 && Z == 0)
|
{
|
{
|
OUTS (outf, regs_hi (reg, grp));
|
OUTS (outf, regs_hi (reg, grp));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, huimm16 (hword));
|
OUTS (outf, uimm16 (hword));
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
|
|
|
/* And we print out the 32-bit value if it is a pointer. */
|
|
if (S == 0 && Z == 0)
|
|
{
|
|
OUTS (outf, ";\t\t/* (");
|
|
OUTS (outf, imm16d (hword));
|
|
OUTS (outf, ")\t");
|
|
|
|
/* If it is an MMR, don't print the symbol. */
|
|
if (*pval < 0xFFC00000 && grp == 1)
|
|
{
|
|
OUTS (outf, regs (reg, grp));
|
|
OUTS (outf, "=0x");
|
|
OUTS (outf, huimm32e (*pval));
|
|
}
|
|
else
|
|
{
|
|
OUTS (outf, regs (reg, grp));
|
|
OUTS (outf, "=0x");
|
|
OUTS (outf, huimm32e (*pval));
|
|
OUTS (outf, "(");
|
|
OUTS (outf, imm32 (*pval));
|
|
OUTS (outf, ")");
|
|
}
|
|
|
|
OUTS (outf, " */");
|
|
comment = 1;
|
|
}
|
|
if (S == 1 || Z == 1)
|
|
{
|
|
OUTS (outf, ";\t\t/*\t\t");
|
|
OUTS (outf, regs (reg, grp));
|
|
OUTS (outf, "=0x");
|
|
OUTS (outf, huimm32e (*pval));
|
|
OUTS (outf, "(");
|
|
OUTS (outf, imm32 (*pval));
|
|
OUTS (outf, ") */");
|
|
comment = 1;
|
|
}
|
return 4;
|
return 4;
|
}
|
}
|
|
|
static int
|
static int
|
decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
|
decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
|
| Line 2406... |
Line 2731... |
int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
|
int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
|
int lsw = ((iw1 >> 0) & 0xffff);
|
int lsw = ((iw1 >> 0) & 0xffff);
|
int msw = ((iw0 >> 0) & 0xff);
|
int msw = ((iw0 >> 0) & 0xff);
|
|
|
if (S == 1)
|
if (S == 1)
|
OUTS (outf, "CALL ");
|
OUTS (outf, "CALL 0x");
|
else if (S == 0)
|
else if (S == 0)
|
OUTS (outf, "JUMP.L ");
|
OUTS (outf, "JUMP.L 0x");
|
else
|
else
|
return 0;
|
return 0;
|
|
|
OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
|
OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
|
return 4;
|
return 4;
|
| Line 2542... |
Line 2867... |
|
|
if (R == 0)
|
if (R == 0)
|
{
|
{
|
OUTS (outf, "LINK ");
|
OUTS (outf, "LINK ");
|
OUTS (outf, uimm16s4 (framesize));
|
OUTS (outf, uimm16s4 (framesize));
|
|
OUTS (outf, ";\t\t/* (");
|
|
OUTS (outf, uimm16s4d (framesize));
|
|
OUTS (outf, ") */");
|
|
comment = 1;
|
}
|
}
|
else if (R == 1)
|
else if (R == 1)
|
OUTS (outf, "UNLINK");
|
OUTS (outf, "UNLINK");
|
else
|
else
|
return 0;
|
return 0;
|
| Line 2583... |
Line 2912... |
return 0;
|
return 0;
|
|
|
if ((w1 || w0) && mmod == M_W32)
|
if ((w1 || w0) && mmod == M_W32)
|
return 0;
|
return 0;
|
|
|
if (((1 << mmod) & (P ? 0x31b : 0x1b5f)) == 0)
|
if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
|
return 0;
|
return 0;
|
|
|
if (w1 == 1 || op1 != 3)
|
if (w1 == 1 || op1 != 3)
|
{
|
{
|
if (w1)
|
if (w1)
|
| Line 2803... |
Line 3132... |
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 1 && aop == 1 && aopcde == 2)
|
else if (HL == 1 && aop == 1 && aopcde == 2)
|
{
|
{
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 1 && aop == 2 && aopcde == 2)
|
else if (HL == 1 && aop == 2 && aopcde == 2)
|
{
|
{
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 1 && aop == 3 && aopcde == 2)
|
else if (HL == 1 && aop == 3 && aopcde == 2)
|
{
|
{
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 0 && aop == 0 && aopcde == 3)
|
else if (HL == 0 && aop == 0 && aopcde == 3)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 0 && aop == 1 && aopcde == 3)
|
else if (HL == 0 && aop == 1 && aopcde == 3)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 0 && aop == 3 && aopcde == 2)
|
else if (HL == 0 && aop == 3 && aopcde == 2)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 1 && aop == 0 && aopcde == 3)
|
else if (HL == 1 && aop == 0 && aopcde == 3)
|
{
|
{
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 1 && aop == 1 && aopcde == 3)
|
else if (HL == 1 && aop == 1 && aopcde == 3)
|
{
|
{
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 1 && aop == 2 && aopcde == 3)
|
else if (HL == 1 && aop == 2 && aopcde == 3)
|
{
|
{
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 1 && aop == 3 && aopcde == 3)
|
else if (HL == 1 && aop == 3 && aopcde == 3)
|
{
|
{
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, dregs_hi (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 0 && aop == 2 && aopcde == 2)
|
else if (HL == 0 && aop == 2 && aopcde == 2)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 0 && aop == 1 && aopcde == 2)
|
else if (HL == 0 && aop == 1 && aopcde == 2)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 0 && aop == 2 && aopcde == 3)
|
else if (HL == 0 && aop == 2 && aopcde == 3)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 0 && aop == 3 && aopcde == 3)
|
else if (HL == 0 && aop == 3 && aopcde == 3)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, dregs_hi (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 0 && aop == 0 && aopcde == 2)
|
else if (HL == 0 && aop == 0 && aopcde == 2)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (aop == 0 && aopcde == 9 && s == 1)
|
else if (aop == 0 && aopcde == 9 && s == 1)
|
{
|
{
|
OUTS (outf, "A0=");
|
OUTS (outf, "A0=");
|
| Line 3041... |
Line 3354... |
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=BYTEOP2P(");
|
OUTS (outf, "=BYTEOP2P(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ")(TH");
|
OUTS (outf, ")(TH");
|
if (s == 1)
|
if (s == 1)
|
OUTS (outf, ", R)");
|
OUTS (outf, ", R)");
|
else
|
else
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
| Line 3058... |
Line 3371... |
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=BYTEOP2P(");
|
OUTS (outf, "=BYTEOP2P(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ")(TL");
|
OUTS (outf, ")(TL");
|
if (s == 1)
|
if (s == 1)
|
OUTS (outf, ", R)");
|
OUTS (outf, ", R)");
|
else
|
else
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
| Line 3075... |
Line 3388... |
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=BYTEOP2P(");
|
OUTS (outf, "=BYTEOP2P(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ")(RNDH");
|
OUTS (outf, ")(RNDH");
|
if (s == 1)
|
if (s == 1)
|
OUTS (outf, ", R)");
|
OUTS (outf, ", R)");
|
else
|
else
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
| Line 3092... |
Line 3405... |
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=BYTEOP2P(");
|
OUTS (outf, "=BYTEOP2P(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ")(RNDL");
|
OUTS (outf, ")(RNDL");
|
if (s == 1)
|
if (s == 1)
|
OUTS (outf, ", R)");
|
OUTS (outf, ", R)");
|
else
|
else
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
| Line 3129... |
Line 3442... |
else if (aop == 3 && s == 1 && aopcde == 8)
|
else if (aop == 3 && s == 1 && aopcde == 8)
|
OUTS (outf, "A1=A0");
|
OUTS (outf, "A1=A0");
|
|
|
else if (aop == 1 && aopcde == 9 && s == 0)
|
else if (aop == 1 && aopcde == 9 && s == 0)
|
{
|
{
|
OUTS (outf, "A0.x=");
|
OUTS (outf, "A0.X = ");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
}
|
}
|
else if (aop == 1 && HL == 0 && aopcde == 11)
|
else if (aop == 1 && HL == 0 && aopcde == 11)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
| Line 3146... |
Line 3459... |
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=BYTEOP3P(");
|
OUTS (outf, "=BYTEOP3P(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ")(HI");
|
OUTS (outf, ")(HI");
|
if (s == 1)
|
if (s == 1)
|
OUTS (outf, ", R)");
|
OUTS (outf, ", R)");
|
else
|
else
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
else if (aop == 3 && aopcde == 9 && s == 0)
|
else if (aop == 3 && aopcde == 9 && s == 0)
|
{
|
{
|
OUTS (outf, "A1.x=");
|
OUTS (outf, "A1.X = ");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
}
|
}
|
else if (aop == 1 && HL == 1 && aopcde == 16)
|
else if (aop == 1 && HL == 1 && aopcde == 16)
|
OUTS (outf, "A1= ABS A1");
|
OUTS (outf, "A1= ABS A1");
|
|
|
| Line 3234... |
Line 3547... |
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=BYTEOP3P(");
|
OUTS (outf, "=BYTEOP3P(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ")(LO");
|
OUTS (outf, ")(LO");
|
if (s == 1)
|
if (s == 1)
|
OUTS (outf, ", R)");
|
OUTS (outf, ", R)");
|
else
|
else
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
| Line 3270... |
Line 3583... |
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, dregs_hi (src1));
|
OUTS (outf, "+SIGN(");
|
OUTS (outf, "+SIGN(");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, ")*");
|
OUTS (outf, ")*");
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, ")");
|
|
}
|
}
|
else if (aop == 2 && aopcde == 0)
|
else if (aop == 2 && aopcde == 0)
|
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs (src0));
|
OUTS (outf, dregs (src0));
|
OUTS (outf, "-|+");
|
OUTS (outf, "-|+");
|
OUTS (outf, dregs (src1));
|
OUTS (outf, dregs (src1));
|
OUTS (outf, " ");
|
|
amod0 (s, x, outf);
|
amod0 (s, x, outf);
|
}
|
}
|
else if (aop == 1 && aopcde == 12)
|
else if (aop == 1 && aopcde == 12)
|
{
|
{
|
OUTS (outf, dregs (dst1));
|
OUTS (outf, dregs (dst1));
|
| Line 3302... |
Line 3613... |
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs (src0));
|
OUTS (outf, dregs (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs (src1));
|
OUTS (outf, dregs (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (HL == 0 && aopcde == 1)
|
else if (HL == 0 && aopcde == 1)
|
{
|
{
|
OUTS (outf, dregs (dst1));
|
OUTS (outf, dregs (dst1));
|
| Line 3328... |
Line 3638... |
OUTS (outf, "=(A0+=A1)");
|
OUTS (outf, "=(A0+=A1)");
|
}
|
}
|
else if (aop == 0 && aopcde == 10)
|
else if (aop == 0 && aopcde == 10)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=A0.x");
|
OUTS (outf, " = A0.X");
|
}
|
}
|
else if (aop == 1 && aopcde == 10)
|
else if (aop == 1 && aopcde == 10)
|
{
|
{
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, dregs_lo (dst0));
|
OUTS (outf, "=A1.x");
|
OUTS (outf, " = A1.X");
|
}
|
}
|
else if (aop == 1 && aopcde == 0)
|
else if (aop == 1 && aopcde == 0)
|
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs (src0));
|
OUTS (outf, dregs (src0));
|
OUTS (outf, "+|-");
|
OUTS (outf, "+|-");
|
OUTS (outf, dregs (src1));
|
OUTS (outf, dregs (src1));
|
OUTS (outf, " ");
|
|
amod0 (s, x, outf);
|
amod0 (s, x, outf);
|
}
|
}
|
else if (aop == 3 && aopcde == 0)
|
else if (aop == 3 && aopcde == 0)
|
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs (src0));
|
OUTS (outf, dregs (src0));
|
OUTS (outf, "-|-");
|
OUTS (outf, "-|-");
|
OUTS (outf, dregs (src1));
|
OUTS (outf, dregs (src1));
|
OUTS (outf, " ");
|
|
amod0 (s, x, outf);
|
amod0 (s, x, outf);
|
}
|
}
|
else if (aop == 1 && aopcde == 4)
|
else if (aop == 1 && aopcde == 4)
|
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs (src0));
|
OUTS (outf, dregs (src0));
|
OUTS (outf, "-");
|
OUTS (outf, "-");
|
OUTS (outf, dregs (src1));
|
OUTS (outf, dregs (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (aop == 0 && aopcde == 17)
|
else if (aop == 0 && aopcde == 17)
|
{
|
{
|
OUTS (outf, dregs (dst1));
|
OUTS (outf, dregs (dst1));
|
| Line 3386... |
Line 3693... |
else if (aop == 0 && aopcde == 18)
|
else if (aop == 0 && aopcde == 18)
|
{
|
{
|
OUTS (outf, "SAA(");
|
OUTS (outf, "SAA(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ") ");
|
OUTS (outf, ") ");
|
aligndir (s, outf);
|
aligndir (s, outf);
|
}
|
}
|
else if (aop == 3 && aopcde == 18)
|
else if (aop == 3 && aopcde == 18)
|
OUTS (outf, "DISALGNEXCPT");
|
OUTS (outf, "DISALGNEXCPT");
|
| Line 3403... |
Line 3710... |
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=BYTEOP1P(");
|
OUTS (outf, "=BYTEOP1P(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
aligndir (s, outf);
|
aligndir (s, outf);
|
}
|
}
|
else if (aop == 1 && aopcde == 20)
|
else if (aop == 1 && aopcde == 20)
|
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=BYTEOP1P(");
|
OUTS (outf, "=BYTEOP1P(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ")(T");
|
OUTS (outf, ")(T");
|
if (s == 1)
|
if (s == 1)
|
OUTS (outf, ", R)");
|
OUTS (outf, ", R)");
|
else
|
else
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
| Line 3437... |
Line 3744... |
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, ")=BYTEOP16P(");
|
OUTS (outf, ")=BYTEOP16P(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ") ");
|
OUTS (outf, ") ");
|
aligndir (s, outf);
|
aligndir (s, outf);
|
}
|
}
|
else if (aop == 1 && aopcde == 21)
|
else if (aop == 1 && aopcde == 21)
|
{
|
{
|
| Line 3454... |
Line 3761... |
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, ")=BYTEOP16M(");
|
OUTS (outf, ")=BYTEOP16M(");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, dregs (src1 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src1));
|
OUTS (outf, imm5d (src1));
|
OUTS (outf, ") ");
|
OUTS (outf, ") ");
|
aligndir (s, outf);
|
aligndir (s, outf);
|
}
|
}
|
else if (aop == 2 && aopcde == 7)
|
else if (aop == 2 && aopcde == 7)
|
{
|
{
|
| Line 3533... |
Line 3840... |
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs (src0));
|
OUTS (outf, dregs (src0));
|
OUTS (outf, "+");
|
OUTS (outf, "+");
|
OUTS (outf, dregs (src1));
|
OUTS (outf, dregs (src1));
|
OUTS (outf, " ");
|
|
amod1 (s, x, outf);
|
amod1 (s, x, outf);
|
}
|
}
|
else if (aop == 0 && aopcde == 0)
|
else if (aop == 0 && aopcde == 0)
|
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=");
|
OUTS (outf, "=");
|
OUTS (outf, dregs (src0));
|
OUTS (outf, dregs (src0));
|
OUTS (outf, "+|+");
|
OUTS (outf, "+|+");
|
OUTS (outf, dregs (src1));
|
OUTS (outf, dregs (src1));
|
OUTS (outf, " ");
|
|
amod0 (s, x, outf);
|
amod0 (s, x, outf);
|
}
|
}
|
else if (aop == 0 && aopcde == 24)
|
else if (aop == 0 && aopcde == 24)
|
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
| Line 3564... |
Line 3869... |
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, ") = BYTEUNPACK ");
|
OUTS (outf, ") = BYTEUNPACK ");
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, dregs (src0 + 1));
|
OUTS (outf, ":");
|
OUTS (outf, ":");
|
OUTS (outf, imm5 (src0));
|
OUTS (outf, imm5d (src0));
|
OUTS (outf, " ");
|
|
aligndir (s, outf);
|
aligndir (s, outf);
|
}
|
}
|
else if (aopcde == 13)
|
else if (aopcde == 13)
|
{
|
{
|
OUTS (outf, "(");
|
OUTS (outf, "(");
|
| Line 3773... |
Line 4077... |
OUTS (outf, "(V)");
|
OUTS (outf, "(V)");
|
}
|
}
|
else if (sop == 0 && sopcde == 4)
|
else if (sop == 0 && sopcde == 4)
|
{
|
{
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, dregs (dst0));
|
OUTS (outf, "=PACK");
|
OUTS (outf, " = PACK (");
|
OUTS (outf, "(");
|
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, dregs_lo (src1));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, dregs_lo (src0));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
| Line 4269... |
Line 4572... |
static int
|
static int
|
decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
|
decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
|
{
|
{
|
/* pseudodbg_assert
|
/* pseudodbg_assert
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
|
| 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
|
| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
|
|.expected......................................................|
|
|.expected......................................................|
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
|
int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
|
int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
|
int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
|
int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
|
|
int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
|
int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
|
int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
|
|
|
if (dbgop == 0)
|
if (dbgop == 0)
|
{
|
{
|
OUTS (outf, "DBGA(");
|
OUTS (outf, "DBGA(");
|
OUTS (outf, dregs_lo (regtest));
|
OUTS (outf, regs_lo (regtest, grp));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, uimm16 (expected));
|
OUTS (outf, uimm16 (expected));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
else if (dbgop == 1)
|
else if (dbgop == 1)
|
{
|
{
|
OUTS (outf, "DBGA(");
|
OUTS (outf, "DBGA(");
|
OUTS (outf, dregs_hi (regtest));
|
OUTS (outf, regs_hi (regtest, grp));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, uimm16 (expected));
|
OUTS (outf, uimm16 (expected));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
else if (dbgop == 2)
|
else if (dbgop == 2)
|
{
|
{
|
OUTS (outf, "DBGAL(");
|
OUTS (outf, "DBGAL(");
|
OUTS (outf, dregs (regtest));
|
OUTS (outf, allregs (regtest, grp));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, uimm16 (expected));
|
OUTS (outf, uimm16 (expected));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
else if (dbgop == 3)
|
else if (dbgop == 3)
|
{
|
{
|
OUTS (outf, "DBGAH(");
|
OUTS (outf, "DBGAH(");
|
OUTS (outf, dregs (regtest));
|
OUTS (outf, allregs (regtest, grp));
|
OUTS (outf, ",");
|
OUTS (outf, ",");
|
OUTS (outf, uimm16 (expected));
|
OUTS (outf, uimm16 (expected));
|
OUTS (outf, ")");
|
OUTS (outf, ")");
|
}
|
}
|
else
|
else
|
return 0;
|
return 0;
|
return 4;
|
return 4;
|
}
|
}
|
|
|
int
|
static int
|
_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
|
_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
|
{
|
{
|
bfd_byte buf[4];
|
bfd_byte buf[4];
|
TIword iw0;
|
TIword iw0;
|
TIword iw1;
|
TIword iw1;
|
| Line 4330... |
Line 4634... |
iw0 = bfd_getl16 (buf);
|
iw0 = bfd_getl16 (buf);
|
iw1 = bfd_getl16 (buf + 2);
|
iw1 = bfd_getl16 (buf + 2);
|
|
|
if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
|
if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
|
{
|
{
|
OUTS (outf, "mnop");
|
OUTS (outf, "MNOP");
|
return 4;
|
return 4;
|
}
|
}
|
else if ((iw0 & 0xff00) == 0x0000)
|
else if ((iw0 & 0xff00) == 0x0000)
|
rv = decode_ProgCtrl_0 (iw0, outf);
|
rv = decode_ProgCtrl_0 (iw0, outf);
|
else if ((iw0 & 0xffc0) == 0x0240)
|
else if ((iw0 & 0xffc0) == 0x0240)
|
| Line 4407... |
Line 4711... |
rv = decode_pseudoDEBUG_0 (iw0, outf);
|
rv = decode_pseudoDEBUG_0 (iw0, outf);
|
#if 0
|
#if 0
|
else if ((iw0 & 0xFF00) == 0xF900)
|
else if ((iw0 & 0xFF00) == 0xF900)
|
rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
|
rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
|
#endif
|
#endif
|
else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)
|
else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
|
rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
|
rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
|
|
|
return rv;
|
return rv;
|
}
|
}
|
|
|
| Line 4432... |
Line 4736... |
/* Proper display of multiple issue instructions. */
|
/* Proper display of multiple issue instructions. */
|
|
|
if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
|
if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
|
&& ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
|
&& ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
|
{
|
{
|
|
parallel = 1;
|
outf->fprintf_func (outf->stream, " || ");
|
outf->fprintf_func (outf->stream, " || ");
|
count += _print_insn_bfin (pc + 4, outf);
|
count += _print_insn_bfin (pc + 4, outf);
|
outf->fprintf_func (outf->stream, " || ");
|
outf->fprintf_func (outf->stream, " || ");
|
count += _print_insn_bfin (pc + 6, outf);
|
count += _print_insn_bfin (pc + 6, outf);
|
|
parallel = 0;
|
}
|
}
|
if (count == 0)
|
if (count == 0)
|
{
|
{
|
outf->fprintf_func (outf->stream, "ILLEGAL");
|
outf->fprintf_func (outf->stream, "ILLEGAL");
|
return 2;
|
return 2;
|
}
|
}
|
|
if (!comment)
|
outf->fprintf_func (outf->stream, ";");
|
outf->fprintf_func (outf->stream, ";");
|
|
|
|
comment = 0;
|
|
|
return count;
|
return count;
|
}
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
