| Line 1... |
Line 1... |
/* Declarations for Intel 80386 opcode table
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/* Declarations for Intel 80386 opcode table
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Copyright 2007, 2008
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Copyright 2007, 2008, 2009
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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This library is free software; you can redistribute it and/or modify
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| Line 40... |
Line 40... |
#define Cpu486 (Cpu386 + 1)
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#define Cpu486 (Cpu386 + 1)
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/* i585 or better required */
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/* i585 or better required */
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#define Cpu586 (Cpu486 + 1)
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#define Cpu586 (Cpu486 + 1)
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/* i686 or better required */
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/* i686 or better required */
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#define Cpu686 (Cpu586 + 1)
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#define Cpu686 (Cpu586 + 1)
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/* Pentium4 or better required */
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/* CLFLUSH Instuction support required */
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#define CpuP4 (Cpu686 + 1)
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#define CpuClflush (Cpu686 + 1)
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/* AMD K6 or better required*/
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/* SYSCALL Instuctions support required */
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#define CpuK6 (CpuP4 + 1)
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#define CpuSYSCALL (CpuClflush + 1)
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/* AMD K8 or better required */
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/* Floating point support required */
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#define CpuK8 (CpuK6 + 1)
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#define Cpu8087 (CpuSYSCALL + 1)
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/* i287 support required */
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#define Cpu287 (Cpu8087 + 1)
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/* i387 support required */
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#define Cpu387 (Cpu287 + 1)
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/* i686 and floating point support required */
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#define Cpu687 (Cpu387 + 1)
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/* SSE3 and floating point support required */
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#define CpuFISTTP (Cpu687 + 1)
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/* MMX support required */
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/* MMX support required */
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#define CpuMMX (CpuK8 + 1)
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#define CpuMMX (CpuFISTTP + 1)
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/* SSE support required */
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/* SSE support required */
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#define CpuSSE (CpuMMX + 1)
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#define CpuSSE (CpuMMX + 1)
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/* SSE2 support required */
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/* SSE2 support required */
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#define CpuSSE2 (CpuSSE + 1)
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#define CpuSSE2 (CpuSSE + 1)
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/* 3dnow! support required */
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/* 3dnow! support required */
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| Line 76... |
Line 84... |
#define CpuABM (CpuSSE4a + 1)
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#define CpuABM (CpuSSE4a + 1)
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/* SSE4.1 support required */
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/* SSE4.1 support required */
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#define CpuSSE4_1 (CpuABM + 1)
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#define CpuSSE4_1 (CpuABM + 1)
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/* SSE4.2 support required */
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/* SSE4.2 support required */
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#define CpuSSE4_2 (CpuSSE4_1 + 1)
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#define CpuSSE4_2 (CpuSSE4_1 + 1)
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/* SSE5 support required */
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/* AVX support required */
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#define CpuSSE5 (CpuSSE4_2 + 1)
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#define CpuAVX (CpuSSE4_2 + 1)
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/* Intel L1OM support required */
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#define CpuL1OM (CpuAVX + 1)
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/* Xsave/xrstor New Instuctions support required */
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/* Xsave/xrstor New Instuctions support required */
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#define CpuXsave (CpuSSE5 + 1)
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#define CpuXsave (CpuL1OM + 1)
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/* AES support required */
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#define CpuAES (CpuXsave + 1)
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/* PCLMUL support required */
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#define CpuPCLMUL (CpuAES + 1)
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/* FMA support required */
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#define CpuFMA (CpuPCLMUL + 1)
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/* FMA4 support required */
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#define CpuFMA4 (CpuFMA + 1)
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/* MOVBE Instuction support required */
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#define CpuMovbe (CpuFMA4 + 1)
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/* EPT Instructions required */
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#define CpuEPT (CpuMovbe + 1)
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/* RDTSCP Instuction support required */
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#define CpuRdtscp (CpuEPT + 1)
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/* 64bit support available, used by -march= in assembler. */
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/* 64bit support available, used by -march= in assembler. */
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#define CpuLM (CpuXsave + 1)
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#define CpuLM (CpuRdtscp + 1)
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/* 64bit support required */
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/* 64bit support required */
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#define Cpu64 (CpuLM + 1)
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#define Cpu64 (CpuLM + 1)
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/* Not supported in the 64bit mode */
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/* Not supported in the 64bit mode */
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#define CpuNo64 (Cpu64 + 1)
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#define CpuNo64 (Cpu64 + 1)
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/* The last bitfield in i386_cpu_flags. */
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/* The last bitfield in i386_cpu_flags. */
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| Line 110... |
Line 134... |
unsigned int cpui286:1;
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unsigned int cpui286:1;
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unsigned int cpui386:1;
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unsigned int cpui386:1;
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unsigned int cpui486:1;
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unsigned int cpui486:1;
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unsigned int cpui586:1;
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unsigned int cpui586:1;
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unsigned int cpui686:1;
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unsigned int cpui686:1;
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unsigned int cpup4:1;
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unsigned int cpuclflush:1;
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unsigned int cpuk6:1;
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unsigned int cpusyscall:1;
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unsigned int cpuk8:1;
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unsigned int cpu8087:1;
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unsigned int cpu287:1;
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unsigned int cpu387:1;
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unsigned int cpu687:1;
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unsigned int cpufisttp:1;
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unsigned int cpummx:1;
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unsigned int cpummx:1;
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unsigned int cpusse:1;
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unsigned int cpusse:1;
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unsigned int cpusse2:1;
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unsigned int cpusse2:1;
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unsigned int cpua3dnow:1;
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unsigned int cpua3dnow:1;
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unsigned int cpua3dnowa:1;
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unsigned int cpua3dnowa:1;
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| Line 128... |
Line 156... |
unsigned int cpussse3:1;
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unsigned int cpussse3:1;
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unsigned int cpusse4a:1;
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unsigned int cpusse4a:1;
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unsigned int cpuabm:1;
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unsigned int cpuabm:1;
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unsigned int cpusse4_1:1;
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unsigned int cpusse4_1:1;
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unsigned int cpusse4_2:1;
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unsigned int cpusse4_2:1;
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unsigned int cpusse5:1;
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unsigned int cpuavx:1;
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unsigned int cpul1om:1;
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unsigned int cpuxsave:1;
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unsigned int cpuxsave:1;
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unsigned int cpuaes:1;
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unsigned int cpupclmul:1;
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unsigned int cpufma:1;
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unsigned int cpufma4:1;
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unsigned int cpumovbe:1;
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unsigned int cpuept:1;
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unsigned int cpurdtscp:1;
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unsigned int cpulm:1;
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unsigned int cpulm:1;
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unsigned int cpu64:1;
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unsigned int cpu64:1;
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unsigned int cpuno64:1;
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unsigned int cpuno64:1;
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#ifdef CpuUnused
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#ifdef CpuUnused
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unsigned int unused:(CpuNumOfBits - CpuUnused);
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unsigned int unused:(CpuNumOfBits - CpuUnused);
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| Line 146... |
Line 182... |
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/* has direction bit. */
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/* has direction bit. */
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#define D 0
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#define D 0
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/* set if operands can be words or dwords encoded the canonical way */
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/* set if operands can be words or dwords encoded the canonical way */
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#define W (D + 1)
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#define W (D + 1)
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/* Skip the current insn and use the next insn in i386-opc.tbl to swap
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operand in encoding. */
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#define S (W + 1)
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/* insn has a modrm byte. */
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/* insn has a modrm byte. */
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#define Modrm (W + 1)
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#define Modrm (S + 1)
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/* register is in low 3 bits of opcode */
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/* register is in low 3 bits of opcode */
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#define ShortForm (Modrm + 1)
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#define ShortForm (Modrm + 1)
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/* special case for jump insns. */
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/* special case for jump insns. */
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#define Jump (ShortForm + 1)
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#define Jump (ShortForm + 1)
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/* call and jump */
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/* call and jump */
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| Line 196... |
Line 235... |
/* fake an extra reg operand for clr, imul and special register
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/* fake an extra reg operand for clr, imul and special register
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processing for some instructions. */
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processing for some instructions. */
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#define RegKludge (IsString + 1)
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#define RegKludge (IsString + 1)
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/* The first operand must be xmm0 */
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/* The first operand must be xmm0 */
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#define FirstXmm0 (RegKludge + 1)
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#define FirstXmm0 (RegKludge + 1)
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/* An implicit xmm0 as the first operand */
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#define Implicit1stXmm0 (FirstXmm0 + 1)
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/* BYTE is OK in Intel syntax. */
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/* BYTE is OK in Intel syntax. */
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#define ByteOkIntel (FirstXmm0 + 1)
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#define ByteOkIntel (Implicit1stXmm0 + 1)
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/* Convert to DWORD */
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/* Convert to DWORD */
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#define ToDword (ByteOkIntel + 1)
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#define ToDword (ByteOkIntel + 1)
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/* Convert to QWORD */
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/* Convert to QWORD */
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#define ToQword (ToDword + 1)
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#define ToQword (ToDword + 1)
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/* Address prefix changes operand 0 */
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/* Address prefix changes operand 0 */
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| Line 214... |
Line 255... |
#define NoRex64 (ImmExt + 1)
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#define NoRex64 (ImmExt + 1)
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/* instruction require Rex64 prefix. */
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/* instruction require Rex64 prefix. */
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#define Rex64 (NoRex64 + 1)
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#define Rex64 (NoRex64 + 1)
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/* deprecated fp insn, gets a warning */
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/* deprecated fp insn, gets a warning */
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#define Ugh (Rex64 + 1)
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#define Ugh (Rex64 + 1)
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#define Drex (Ugh + 1)
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/* insn has VEX prefix. */
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/* instruction needs DREX with multiple encodings for memory ops */
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#define Vex (Ugh + 1)
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#define Drexv (Drex + 1)
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/* insn has 256bit VEX prefix. */
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/* special DREX for comparisons */
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#define Vex256 (Vex + 1)
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#define Drexc (Drexv + 1)
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/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
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We use VexNDS on insns with VEX DDS since the register-only source
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is the second source register. */
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#define VexNDS (Vex256 + 1)
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/* insn has VEX NDD. Register destination is encoded in Vex
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prefix. */
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#define VexNDD (VexNDS + 1)
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/* insn has VEX W0. */
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#define VexW0 (VexNDD + 1)
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/* insn has VEX W1. */
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#define VexW1 (VexW0 + 1)
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/* insn has VEX 0x0F opcode prefix. */
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#define Vex0F (VexW1 + 1)
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/* insn has VEX 0x0F38 opcode prefix. */
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#define Vex0F38 (Vex0F + 1)
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/* insn has VEX 0x0F3A opcode prefix. */
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#define Vex0F3A (Vex0F38 + 1)
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/* insn has VEX prefix with 3 soures. */
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#define Vex3Sources (Vex0F3A + 1)
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/* instruction has VEX 8 bit imm */
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#define VexImmExt (Vex3Sources + 1)
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/* SSE to AVX support required */
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#define SSE2AVX (VexImmExt + 1)
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/* No AVX equivalent */
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#define NoAVX (SSE2AVX + 1)
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/* Compatible with old (<= 2.8.1) versions of gcc */
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/* Compatible with old (<= 2.8.1) versions of gcc */
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#define OldGcc (Drexc + 1)
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#define OldGcc (NoAVX + 1)
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/* AT&T mnemonic. */
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/* AT&T mnemonic. */
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#define ATTMnemonic (OldGcc + 1)
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#define ATTMnemonic (OldGcc + 1)
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/* AT&T syntax. */
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/* AT&T syntax. */
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#define ATTSyntax (ATTMnemonic + 1)
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#define ATTSyntax (ATTMnemonic + 1)
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/* Intel syntax. */
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/* Intel syntax. */
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| Line 234... |
Line 299... |
|
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typedef struct i386_opcode_modifier
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typedef struct i386_opcode_modifier
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{
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{
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unsigned int d:1;
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unsigned int d:1;
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unsigned int w:1;
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unsigned int w:1;
|
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unsigned int s:1;
|
unsigned int modrm:1;
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unsigned int modrm:1;
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unsigned int shortform:1;
|
unsigned int shortform:1;
|
unsigned int jump:1;
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unsigned int jump:1;
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unsigned int jumpdword:1;
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unsigned int jumpdword:1;
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unsigned int jumpbyte:1;
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unsigned int jumpbyte:1;
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| Line 258... |
Line 324... |
unsigned int no_ldsuf:1;
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unsigned int no_ldsuf:1;
|
unsigned int fwait:1;
|
unsigned int fwait:1;
|
unsigned int isstring:1;
|
unsigned int isstring:1;
|
unsigned int regkludge:1;
|
unsigned int regkludge:1;
|
unsigned int firstxmm0:1;
|
unsigned int firstxmm0:1;
|
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unsigned int implicit1stxmm0:1;
|
unsigned int byteokintel:1;
|
unsigned int byteokintel:1;
|
unsigned int todword:1;
|
unsigned int todword:1;
|
unsigned int toqword:1;
|
unsigned int toqword:1;
|
unsigned int addrprefixop0:1;
|
unsigned int addrprefixop0:1;
|
unsigned int isprefix:1;
|
unsigned int isprefix:1;
|
unsigned int immext:1;
|
unsigned int immext:1;
|
unsigned int norex64:1;
|
unsigned int norex64:1;
|
unsigned int rex64:1;
|
unsigned int rex64:1;
|
unsigned int ugh:1;
|
unsigned int ugh:1;
|
unsigned int drex:1;
|
unsigned int vex:1;
|
unsigned int drexv:1;
|
unsigned int vex256:1;
|
unsigned int drexc:1;
|
unsigned int vexnds:1;
|
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unsigned int vexndd:1;
|
|
unsigned int vexw0:1;
|
|
unsigned int vexw1:1;
|
|
unsigned int vex0f:1;
|
|
unsigned int vex0f38:1;
|
|
unsigned int vex0f3a:1;
|
|
unsigned int vex3sources:1;
|
|
unsigned int veximmext:1;
|
|
unsigned int sse2avx:1;
|
|
unsigned int noavx:1;
|
unsigned int oldgcc:1;
|
unsigned int oldgcc:1;
|
unsigned int attmnemonic:1;
|
unsigned int attmnemonic:1;
|
unsigned int attsyntax:1;
|
unsigned int attsyntax:1;
|
unsigned int intelsyntax:1;
|
unsigned int intelsyntax:1;
|
} i386_opcode_modifier;
|
} i386_opcode_modifier;
|
| Line 292... |
Line 369... |
#define FloatReg (Reg64 + 1)
|
#define FloatReg (Reg64 + 1)
|
/* MMX register */
|
/* MMX register */
|
#define RegMMX (FloatReg + 1)
|
#define RegMMX (FloatReg + 1)
|
/* SSE register */
|
/* SSE register */
|
#define RegXMM (RegMMX + 1)
|
#define RegXMM (RegMMX + 1)
|
|
/* AVX registers */
|
|
#define RegYMM (RegXMM + 1)
|
/* Control register */
|
/* Control register */
|
#define Control (RegXMM + 1)
|
#define Control (RegYMM + 1)
|
/* Debug register */
|
/* Debug register */
|
#define Debug (Control + 1)
|
#define Debug (Control + 1)
|
/* Test register */
|
/* Test register */
|
#define Test (Debug + 1)
|
#define Test (Debug + 1)
|
/* 2 bit segment register */
|
/* 2 bit segment register */
|
| Line 369... |
Line 448... |
#define Qword (Fword + 1)
|
#define Qword (Fword + 1)
|
/* TBYTE memory. 10 byte */
|
/* TBYTE memory. 10 byte */
|
#define Tbyte (Qword + 1)
|
#define Tbyte (Qword + 1)
|
/* XMMWORD memory. */
|
/* XMMWORD memory. */
|
#define Xmmword (Tbyte + 1)
|
#define Xmmword (Tbyte + 1)
|
|
/* YMMWORD memory. */
|
|
#define Ymmword (Xmmword + 1)
|
/* Unspecified memory size. */
|
/* Unspecified memory size. */
|
#define Unspecified (Xmmword + 1)
|
#define Unspecified (Ymmword + 1)
|
/* Any memory size. */
|
/* Any memory size. */
|
#define Anysize (Unspecified + 1)
|
#define Anysize (Unspecified + 1)
|
|
|
/* The last bitfield in i386_operand_type. */
|
/* The last bitfield in i386_operand_type. */
|
#define OTMax Anysize
|
#define OTMax Anysize
|
| Line 397... |
Line 478... |
unsigned int reg32:1;
|
unsigned int reg32:1;
|
unsigned int reg64:1;
|
unsigned int reg64:1;
|
unsigned int floatreg:1;
|
unsigned int floatreg:1;
|
unsigned int regmmx:1;
|
unsigned int regmmx:1;
|
unsigned int regxmm:1;
|
unsigned int regxmm:1;
|
|
unsigned int regymm:1;
|
unsigned int control:1;
|
unsigned int control:1;
|
unsigned int debug:1;
|
unsigned int debug:1;
|
unsigned int test:1;
|
unsigned int test:1;
|
unsigned int sreg2:1;
|
unsigned int sreg2:1;
|
unsigned int sreg3:1;
|
unsigned int sreg3:1;
|
| Line 430... |
Line 512... |
unsigned int dword:1;
|
unsigned int dword:1;
|
unsigned int fword:1;
|
unsigned int fword:1;
|
unsigned int qword:1;
|
unsigned int qword:1;
|
unsigned int tbyte:1;
|
unsigned int tbyte:1;
|
unsigned int xmmword:1;
|
unsigned int xmmword:1;
|
|
unsigned int ymmword:1;
|
unsigned int unspecified:1;
|
unsigned int unspecified:1;
|
unsigned int anysize:1;
|
unsigned int anysize:1;
|
#ifdef OTUnused
|
#ifdef OTUnused
|
unsigned int unused:(OTNumOfBits - OTUnused);
|
unsigned int unused:(OTNumOfBits - OTUnused);
|
#endif
|
#endif
|
} bitfield;
|
} bitfield;
|
unsigned int array[OTNumOfUints];
|
unsigned int array[OTNumOfUints];
|
} i386_operand_type;
|
} i386_operand_type;
|
|
|
typedef struct template
|
typedef struct insn_template
|
{
|
{
|
/* instruction name sans width suffix ("mov" for movl insns) */
|
/* instruction name sans width suffix ("mov" for movl insns) */
|
char *name;
|
char *name;
|
|
|
/* how many operands */
|
/* how many operands */
|
| Line 460... |
Line 543... |
|
|
/* extension_opcode is the 3 bit extension for group <n> insns.
|
/* extension_opcode is the 3 bit extension for group <n> insns.
|
This field is also used to store the 8-bit opcode suffix for the
|
This field is also used to store the 8-bit opcode suffix for the
|
AMD 3DNow! instructions.
|
AMD 3DNow! instructions.
|
If this template has no extension opcode (the usual case) use None
|
If this template has no extension opcode (the usual case) use None
|
Instructions with Drex use this to specify 2 bits for OC */
|
Instructions */
|
unsigned int extension_opcode;
|
unsigned int extension_opcode;
|
#define None 0xffff /* If no extension_opcode is possible. */
|
#define None 0xffff /* If no extension_opcode is possible. */
|
|
|
/* Opcode length. */
|
/* Opcode length. */
|
unsigned char opcode_length;
|
unsigned char opcode_length;
|
| Line 481... |
Line 564... |
by OR'ing together all of the possible type masks. (e.g.
|
by OR'ing together all of the possible type masks. (e.g.
|
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
either a register or an immediate operand. */
|
either a register or an immediate operand. */
|
i386_operand_type operand_types[MAX_OPERANDS];
|
i386_operand_type operand_types[MAX_OPERANDS];
|
}
|
}
|
template;
|
insn_template;
|
|
|
extern const template i386_optab[];
|
extern const insn_template i386_optab[];
|
|
|
/* these are for register name --> number & type hash lookup */
|
/* these are for register name --> number & type hash lookup */
|
typedef struct
|
typedef struct
|
{
|
{
|
char *reg_name;
|
char *reg_name;
|
