OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [opcodes/] [ia64-dis.c] - Diff between revs 157 and 225

Show entire file | Details | Blame | View Log

Rev 157 Rev 225
Line 1... Line 1...
/* ia64-dis.c -- Disassemble ia64 instructions
/* ia64-dis.c -- Disassemble ia64 instructions
   Copyright 1998, 1999, 2000, 2002, 2007 Free Software Foundation, Inc.
   Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2008, 2009
 
   Free Software Foundation, Inc.
   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
 
   This file is part of the GNU opcodes library.
   This file is part of the GNU opcodes library.
 
 
   This library is free software; you can redistribute it and/or modify
   This library is free software; you can redistribute it and/or modify
Line 66... Line 67...
}
}
 
 
int
int
print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
{
{
  ia64_insn t0, t1, slot[3], template, s_bit, insn;
  ia64_insn t0, t1, slot[3], template_val, s_bit, insn;
  int slotnum, j, status, need_comma, retval, slot_multiplier;
  int slotnum, j, status, need_comma, retval, slot_multiplier;
  const struct ia64_operand *odesc;
  const struct ia64_operand *odesc;
  const struct ia64_opcode *idesc;
  const struct ia64_opcode *idesc;
  const char *err, *str, *tname;
  const char *err, *str, *tname;
  BFD_HOST_U_64_BIT value;
  BFD_HOST_U_64_BIT value;
Line 98... Line 99...
    }
    }
  /* bundles are always in little-endian byte order */
  /* bundles are always in little-endian byte order */
  t0 = bfd_getl64 (bundle);
  t0 = bfd_getl64 (bundle);
  t1 = bfd_getl64 (bundle + 8);
  t1 = bfd_getl64 (bundle + 8);
  s_bit = t0 & 1;
  s_bit = t0 & 1;
  template = (t0 >> 1) & 0xf;
  template_val = (t0 >> 1) & 0xf;
  slot[0] = (t0 >>  5) & 0x1ffffffffffLL;
  slot[0] = (t0 >>  5) & 0x1ffffffffffLL;
  slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
  slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
  slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
  slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
 
 
  tname = ia64_templ_desc[template].name;
  tname = ia64_templ_desc[template_val].name;
  if (slotnum == 0)
  if (slotnum == 0)
    (*info->fprintf_func) (info->stream, "[%s] ", tname);
    (*info->fprintf_func) (info->stream, "[%s] ", tname);
  else
  else
    (*info->fprintf_func) (info->stream, "      ");
    (*info->fprintf_func) (info->stream, "      ");
 
 
  unit = ia64_templ_desc[template].exec_unit[slotnum];
  unit = ia64_templ_desc[template_val].exec_unit[slotnum];
 
 
  if (template == 2 && slotnum == 1)
  if (template_val == 2 && slotnum == 1)
    {
    {
      /* skip L slot in MLI template: */
      /* skip L slot in MLI template: */
      slotnum = 2;
      slotnum = 2;
      retval += slot_multiplier;
      retval += slot_multiplier;
    }
    }
Line 180... Line 181...
              (*info->fprintf_func) (info->stream, "%s", err);
              (*info->fprintf_func) (info->stream, "%s", err);
              goto done;
              goto done;
            }
            }
        }
        }
 
 
        switch (odesc->class)
        switch (odesc->op_class)
          {
          {
          case IA64_OPND_CLASS_CST:
          case IA64_OPND_CLASS_CST:
            (*info->fprintf_func) (info->stream, "%s", odesc->str);
            (*info->fprintf_func) (info->stream, "%s", odesc->str);
            break;
            break;
 
 
Line 238... Line 239...
                  case 21:      strcpy (regname, "cr.itir"); break;
                  case 21:      strcpy (regname, "cr.itir"); break;
                  case 22:      strcpy (regname, "cr.iipa"); break;
                  case 22:      strcpy (regname, "cr.iipa"); break;
                  case 23:      strcpy (regname, "cr.ifs"); break;
                  case 23:      strcpy (regname, "cr.ifs"); break;
                  case 24:      strcpy (regname, "cr.iim"); break;
                  case 24:      strcpy (regname, "cr.iim"); break;
                  case 25:      strcpy (regname, "cr.iha"); break;
                  case 25:      strcpy (regname, "cr.iha"); break;
 
                  case 26:      strcpy (regname, "cr.iib0"); break;
 
                  case 27:      strcpy (regname, "cr.iib1"); break;
                  case 64:      strcpy (regname, "cr.lid"); break;
                  case 64:      strcpy (regname, "cr.lid"); break;
                  case 65:      strcpy (regname, "cr.ivr"); break;
                  case 65:      strcpy (regname, "cr.ivr"); break;
                  case 66:      strcpy (regname, "cr.tpr"); break;
                  case 66:      strcpy (regname, "cr.tpr"); break;
                  case 67:      strcpy (regname, "cr.eoi"); break;
                  case 67:      strcpy (regname, "cr.eoi"); break;
                  case 68:      strcpy (regname, "cr.irr0"); break;
                  case 68:      strcpy (regname, "cr.irr0"); break;
Line 299... Line 302...
        {
        {
          (*info->fprintf_func) (info->stream, "=");
          (*info->fprintf_func) (info->stream, "=");
          need_comma = 0;
          need_comma = 0;
        }
        }
    }
    }
  if (slotnum + 1 == ia64_templ_desc[template].group_boundary
  if (slotnum + 1 == ia64_templ_desc[template_val].group_boundary
      || ((slotnum == 2) && s_bit))
      || ((slotnum == 2) && s_bit))
    (*info->fprintf_func) (info->stream, ";;");
    (*info->fprintf_func) (info->stream, ";;");
 
 
 done:
 done:
  ia64_free_opcode ((struct ia64_opcode *)idesc);
  ia64_free_opcode ((struct ia64_opcode *)idesc);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.