| Line 1... |
Line 1... |
/* CPU data header for mep.
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/* CPU data header for mep.
|
|
|
THIS FILE IS MACHINE GENERATED WITH CGEN.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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|
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Copyright 1996-2007 Free Software Foundation, Inc.
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Copyright 1996-2009 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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|
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This file is free software; you can redistribute it and/or modify
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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| Line 49... |
Line 49... |
#define CGEN_MAX_INSN_SIZE 4
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#define CGEN_MAX_INSN_SIZE 4
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|
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#define CGEN_INT_INSN_P 1
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#define CGEN_INT_INSN_P 1
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|
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/* Maximum number of syntax elements in an instruction. */
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/* Maximum number of syntax elements in an instruction. */
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#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17
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#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
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|
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/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
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e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
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we can't hash on everything up to the space. */
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we can't hash on everything up to the space. */
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#define CGEN_MNEMONIC_OPERANDS
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#define CGEN_MNEMONIC_OPERANDS
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|
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/* Maximum number of fields in an instruction. */
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/* Maximum number of fields in an instruction. */
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#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 11
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#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10
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|
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/* Enums. */
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/* Enums. */
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|
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/* Enum declaration for major opcodes. */
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/* Enum declaration for major opcodes. */
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typedef enum major {
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typedef enum major {
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| Line 69... |
Line 69... |
, MAJ_4, MAJ_5, MAJ_6, MAJ_7
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, MAJ_4, MAJ_5, MAJ_6, MAJ_7
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, MAJ_8, MAJ_9, MAJ_10, MAJ_11
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, MAJ_8, MAJ_9, MAJ_10, MAJ_11
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, MAJ_12, MAJ_13, MAJ_14, MAJ_15
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, MAJ_12, MAJ_13, MAJ_14, MAJ_15
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} MAJOR;
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} MAJOR;
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|
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/* Enum declaration for condition opcode enum. */
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typedef enum fmax_cond {
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FMAX_F, FMAX_U, FMAX_E, FMAX_UE
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, FMAX_L, FMAX_UL, FMAX_LE, FMAX_ULE
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, FMAX_FI, FMAX_UI, FMAX_EI, FMAX_UEI
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, FMAX_LI, FMAX_ULI, FMAX_LEI, FMAX_ULEI
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} FMAX_COND;
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|
|
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/* Attributes. */
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/* Attributes. */
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|
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/* Enum declaration for machine type selection. */
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/* Enum declaration for machine type selection. */
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typedef enum mach_attr {
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typedef enum mach_attr {
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MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX
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MACH_BASE, MACH_MEP, MACH_H1, MACH_C5
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, MACH_MAX
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} MACH_ATTR;
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} MACH_ATTR;
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|
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/* Enum declaration for instruction set selection. */
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/* Enum declaration for instruction set selection. */
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typedef enum isa_attr {
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typedef enum isa_attr {
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ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2, ISA_EXT_COP2_16
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ISA_MEP, ISA_EXT_CORE1, ISA_EXT_COP1_16, ISA_EXT_COP1_32
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, ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64, ISA_MAX
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, ISA_EXT_COP1_48, ISA_EXT_COP1_64, ISA_MAX
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} ISA_ATTR;
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} ISA_ATTR;
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|
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/* Enum declaration for datatype to use for C intrinsics mapping. */
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/* Enum declaration for datatype to use for C intrinsics mapping. */
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typedef enum cdata_attr {
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typedef enum cdata_attr {
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CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT
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CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT
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, CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT
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, CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT
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, CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT
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, CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT
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} CDATA_ATTR;
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} CDATA_ATTR;
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/* Enum declaration for datatype to use for coprocessor values. */
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typedef enum cptype_attr {
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CPTYPE_CP_DATA_BUS_INT, CPTYPE_VECT, CPTYPE_V2SI, CPTYPE_V4HI
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, CPTYPE_V8QI, CPTYPE_V2USI, CPTYPE_V4UHI, CPTYPE_V8UQI
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} CPTYPE_ATTR;
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/* Enum declaration for Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it.. */
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typedef enum cret_attr {
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CRET_VOID, CRET_FIRST, CRET_FIRSTCOPY
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} CRET_ATTR;
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/* Enum declaration for . */
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/* Enum declaration for . */
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typedef enum config_attr {
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typedef enum config_attr {
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CONFIG_NONE, CONFIG_SIMPLE, CONFIG_FMAX
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CONFIG_NONE, CONFIG_DEFAULT
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} CONFIG_ATTR;
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} CONFIG_ATTR;
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/* Enum declaration for slots for which this opcode is valid - c3, p0s, p0, p1. */
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typedef enum slots_attr {
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SLOTS_CORE, SLOTS_C3, SLOTS_P0S, SLOTS_P0
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, SLOTS_P1
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} SLOTS_ATTR;
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/* Number of architecture variants. */
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/* Number of architecture variants. */
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#define MAX_ISAS ((int) ISA_MAX)
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#define MAX_ISAS ((int) ISA_MAX)
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#define MAX_MACHS ((int) MACH_MAX)
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#define MAX_MACHS ((int) MACH_MAX)
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|
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/* Ifield support. */
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/* Ifield support. */
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| Line 134... |
Line 144... |
|
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/* Enum declaration for mep ifield types. */
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/* Enum declaration for mep ifield types. */
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typedef enum ifield_type {
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typedef enum ifield_type {
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MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN
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MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN
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, MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2
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, MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2
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, MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN
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, MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_EXT4
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, MEP_F_CSRN_HI, MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI
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, MEP_F_EXT62, MEP_F_CRN, MEP_F_CSRN_HI, MEP_F_CSRN_LO
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, MEP_F_CRNX_LO, MEP_F_CRNX, MEP_F_0, MEP_F_1
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, MEP_F_CSRN, MEP_F_CRNX_HI, MEP_F_CRNX_LO, MEP_F_CRNX
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, MEP_F_2, MEP_F_3, MEP_F_4, MEP_F_5
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, MEP_F_0, MEP_F_1, MEP_F_2, MEP_F_3
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, MEP_F_6, MEP_F_7, MEP_F_8, MEP_F_9
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, MEP_F_4, MEP_F_5, MEP_F_6, MEP_F_7
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, MEP_F_10, MEP_F_11, MEP_F_12, MEP_F_13
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, MEP_F_8, MEP_F_9, MEP_F_10, MEP_F_11
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, MEP_F_14, MEP_F_15, MEP_F_16, MEP_F_17
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, MEP_F_12, MEP_F_13, MEP_F_14, MEP_F_15
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, MEP_F_18, MEP_F_19, MEP_F_20, MEP_F_21
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, MEP_F_16, MEP_F_17, MEP_F_18, MEP_F_19
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, MEP_F_22, MEP_F_23, MEP_F_24, MEP_F_25
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, MEP_F_20, MEP_F_21, MEP_F_22, MEP_F_23
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, MEP_F_26, MEP_F_27, MEP_F_28, MEP_F_29
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, MEP_F_24, MEP_F_25, MEP_F_26, MEP_F_27
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, MEP_F_30, MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2
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, MEP_F_28, MEP_F_29, MEP_F_30, MEP_F_31
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, MEP_F_17S16A2, MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N
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, MEP_F_8S8A2, MEP_F_12S4A2, MEP_F_17S16A2, MEP_F_24S5A2N_HI
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, MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6
|
, MEP_F_24S5A2N_LO, MEP_F_24S5A2N, MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO
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, MEP_F_7U9, MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16
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, MEP_F_24U5A2N, MEP_F_2U6, MEP_F_7U9, MEP_F_7U9A2
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, MEP_F_2U10, MEP_F_3U5, MEP_F_4U8, MEP_F_5U8
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, MEP_F_7U9A4, MEP_F_16S16, MEP_F_2U10, MEP_F_3U5
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, MEP_F_5U24, MEP_F_6S8, MEP_F_8S8, MEP_F_16U16
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, MEP_F_4U8, MEP_F_5U8, MEP_F_5U24, MEP_F_6S8
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, MEP_F_12U16, MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2
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, MEP_F_8S8, MEP_F_16U16, MEP_F_12U16, MEP_F_3U29
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, MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO
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, MEP_F_CDISP10, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO, MEP_F_24U8A4N
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, MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N
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, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N, MEP_F_24U4N_HI
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, MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM
|
, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM, MEP_F_CCRN_HI
|
, MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_FMAX_0_4
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, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_C5N4, MEP_F_C5N5
|
, MEP_F_FMAX_4_4, MEP_F_FMAX_8_4, MEP_F_FMAX_12_4, MEP_F_FMAX_16_4
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, MEP_F_C5N6, MEP_F_C5N7, MEP_F_RL5, MEP_F_12S20
|
, MEP_F_FMAX_20_4, MEP_F_FMAX_24_4, MEP_F_FMAX_28_1, MEP_F_FMAX_29_1
|
, MEP_F_C5_RNM, MEP_F_C5_RM, MEP_F_C5_16U16, MEP_F_C5_RMUIMM20
|
, MEP_F_FMAX_30_1, MEP_F_FMAX_31_1, MEP_F_FMAX_FRD, MEP_F_FMAX_FRN
|
, MEP_F_C5_RNMUIMM24, MEP_F_IVC2_2U4, MEP_F_IVC2_3U4, MEP_F_IVC2_8U4
|
, MEP_F_FMAX_FRM, MEP_F_FMAX_RM, MEP_F_MAX
|
, MEP_F_IVC2_8S4, MEP_F_IVC2_1U6, MEP_F_IVC2_2U6, MEP_F_IVC2_3U6
|
|
, MEP_F_IVC2_6U6, MEP_F_IVC2_5U7, MEP_F_IVC2_4U8, MEP_F_IVC2_3U9
|
|
, MEP_F_IVC2_5U16, MEP_F_IVC2_5U21, MEP_F_IVC2_5U26, MEP_F_IVC2_1U31
|
|
, MEP_F_IVC2_4U16, MEP_F_IVC2_4U20, MEP_F_IVC2_4U24, MEP_F_IVC2_4U28
|
|
, MEP_F_IVC2_2U0, MEP_F_IVC2_3U0, MEP_F_IVC2_4U0, MEP_F_IVC2_5U0
|
|
, MEP_F_IVC2_8U0, MEP_F_IVC2_8S0, MEP_F_IVC2_6U2, MEP_F_IVC2_5U3
|
|
, MEP_F_IVC2_4U4, MEP_F_IVC2_3U5, MEP_F_IVC2_5U8, MEP_F_IVC2_4U10
|
|
, MEP_F_IVC2_3U12, MEP_F_IVC2_5U13, MEP_F_IVC2_2U18, MEP_F_IVC2_5U18
|
|
, MEP_F_IVC2_8U20, MEP_F_IVC2_8S20, MEP_F_IVC2_5U23, MEP_F_IVC2_2U23
|
|
, MEP_F_IVC2_3U25, MEP_F_IVC2_IMM16P0, MEP_F_IVC2_SIMM16P0, MEP_F_IVC2_CCRN_C3HI
|
|
, MEP_F_IVC2_CCRN_C3LO, MEP_F_IVC2_CRN, MEP_F_IVC2_CRM, MEP_F_IVC2_CCRN_H1
|
|
, MEP_F_IVC2_CCRN_H2, MEP_F_IVC2_CCRN_LO, MEP_F_IVC2_CMOV1, MEP_F_IVC2_CMOV2
|
|
, MEP_F_IVC2_CMOV3, MEP_F_IVC2_CCRN_C3, MEP_F_IVC2_CCRN, MEP_F_IVC2_CRNX
|
|
, MEP_F_MAX
|
} IFIELD_TYPE;
|
} IFIELD_TYPE;
|
|
|
#define MAX_IFLD ((int) MEP_F_MAX)
|
#define MAX_IFLD ((int) MEP_F_MAX)
|
|
|
/* Hardware attribute indices. */
|
/* Hardware attribute indices. */
|
| Line 188... |
Line 211... |
|
|
/* Enum declaration for mep hardware types. */
|
/* Enum declaration for mep hardware types. */
|
typedef enum cgen_hw_type {
|
typedef enum cgen_hw_type {
|
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
|
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
|
, HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR
|
, HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR
|
, HW_H_CR64, HW_H_CR, HW_H_CCR, HW_H_CR_FMAX
|
, HW_H_CR64, HW_H_CR64_W, HW_H_CR, HW_H_CCR
|
, HW_H_CCR_FMAX, HW_H_FMAX_COMPARE_I_P, HW_MAX
|
, HW_H_CCR_W, HW_H_CR_IVC2, HW_H_CCR_IVC2, HW_MAX
|
} CGEN_HW_TYPE;
|
} CGEN_HW_TYPE;
|
|
|
#define MAX_HW ((int) HW_MAX)
|
#define MAX_HW ((int) HW_MAX)
|
|
|
/* Operand attribute indices. */
|
/* Operand attribute indices. */
|
| Line 242... |
Line 265... |
, MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16
|
, MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16
|
, MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8
|
, MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8
|
, MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3
|
, MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3
|
, MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2
|
, MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2
|
, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
|
, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
|
, MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4
|
, MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4
|
, MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD
|
, MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12
|
, MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT
|
, MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_IVC2_CSAR0
|
, MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR
|
, MEP_OPERAND_IVC2_CC, MEP_OPERAND_IVC2_COFR0, MEP_OPERAND_IVC2_COFR1, MEP_OPERAND_IVC2_COFA0
|
, MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX
|
, MEP_OPERAND_IVC2_COFA1, MEP_OPERAND_IVC2_CSAR1, MEP_OPERAND_IVC2_ACC0_0, MEP_OPERAND_IVC2_ACC0_1
|
|
, MEP_OPERAND_IVC2_ACC0_2, MEP_OPERAND_IVC2_ACC0_3, MEP_OPERAND_IVC2_ACC0_4, MEP_OPERAND_IVC2_ACC0_5
|
|
, MEP_OPERAND_IVC2_ACC0_6, MEP_OPERAND_IVC2_ACC0_7, MEP_OPERAND_IVC2_ACC1_0, MEP_OPERAND_IVC2_ACC1_1
|
|
, MEP_OPERAND_IVC2_ACC1_2, MEP_OPERAND_IVC2_ACC1_3, MEP_OPERAND_IVC2_ACC1_4, MEP_OPERAND_IVC2_ACC1_5
|
|
, MEP_OPERAND_IVC2_ACC1_6, MEP_OPERAND_IVC2_ACC1_7, MEP_OPERAND_CROC, MEP_OPERAND_CRQC
|
|
, MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2, MEP_OPERAND_IVC_X_6_3
|
|
, MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8, MEP_OPERAND_IMM5P7
|
|
, MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4, MEP_OPERAND_IMM3P5
|
|
, MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10, MEP_OPERAND_IMM5P8
|
|
, MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23, MEP_OPERAND_IMM3P25
|
|
, MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_SIMM8P20, MEP_OPERAND_IMM8P20
|
|
, MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP, MEP_OPERAND_IVC_X_0_2
|
|
, MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5, MEP_OPERAND_IMM16P0
|
|
, MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN, MEP_OPERAND_IVC2CCRN
|
|
, MEP_OPERAND_IVC2C3CCRN, MEP_OPERAND_MAX
|
} CGEN_OPERAND_TYPE;
|
} CGEN_OPERAND_TYPE;
|
|
|
/* Number of operands types. */
|
/* Number of operands types. */
|
#define MAX_OPERANDS 90
|
#define MAX_OPERANDS 145
|
|
|
/* Maximum number of operands referenced by any insn. */
|
/* Maximum number of operands referenced by any insn. */
|
#define MAX_OPERAND_INSTANCES 8
|
#define MAX_OPERAND_INSTANCES 8
|
|
|
/* Insn attribute indices. */
|
/* Insn attribute indices. */
|
| Line 268... |
Line 305... |
, CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN
|
, CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN
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, CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN
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, CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN
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, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
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, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
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, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
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, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
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, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
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, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
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, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_END_NBOOLS
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, CGEN_INSN_CPTYPE, CGEN_INSN_CRET, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG
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, CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS
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} CGEN_INSN_ATTR;
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} CGEN_INSN_ATTR;
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/* Number of non-boolean elements in cgen_insn_attr. */
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/* Number of non-boolean elements in cgen_insn_attr. */
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#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
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#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
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/* cgen_insn attribute accessor macros. */
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/* cgen_insn attribute accessor macros. */
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#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
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#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
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#define CGEN_ATTR_CGEN_INSN_CPTYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CPTYPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_CRET_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CRET-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_SLOTS_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SLOTS-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
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#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
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#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
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#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
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#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
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#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
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#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
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#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
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#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
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#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
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Line 371... |
extern CGEN_KEYWORD mep_cgen_opval_h_gpr;
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extern CGEN_KEYWORD mep_cgen_opval_h_gpr;
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extern CGEN_KEYWORD mep_cgen_opval_h_csr;
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extern CGEN_KEYWORD mep_cgen_opval_h_csr;
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extern CGEN_KEYWORD mep_cgen_opval_h_cr64;
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extern CGEN_KEYWORD mep_cgen_opval_h_cr64;
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extern CGEN_KEYWORD mep_cgen_opval_h_cr;
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extern CGEN_KEYWORD mep_cgen_opval_h_cr;
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extern CGEN_KEYWORD mep_cgen_opval_h_ccr;
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extern CGEN_KEYWORD mep_cgen_opval_h_ccr;
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extern CGEN_KEYWORD mep_cgen_opval_h_cr_fmax;
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extern CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2;
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extern CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax;
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extern CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2;
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extern const CGEN_HW_ENTRY mep_cgen_hw_table[];
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extern const CGEN_HW_ENTRY mep_cgen_hw_table[];
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