| Line 1... |
Line 1... |
/* Print mips instructions for GDB, the GNU debugger, or for objdump.
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/* Print mips instructions for GDB, the GNU debugger, or for objdump.
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002, 2003, 2005, 2007, 2008
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2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
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Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
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This file is part of the GNU opcodes library.
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This file is part of the GNU opcodes library.
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| Line 317... |
Line 317... |
{ 29, 1, "c0_datahi_i" },
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{ 29, 1, "c0_datahi_i" },
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{ 29, 2, "c0_taghi_d" },
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{ 29, 2, "c0_taghi_d" },
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{ 29, 3, "c0_datahi_d" },
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{ 29, 3, "c0_datahi_d" },
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};
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};
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/* Xlr cop0 register names. */
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static const char * const mips_cp0_names_xlr[32] = {
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"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
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"c0_context", "c0_pagemask", "c0_wired", "$7",
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"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
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"c0_status", "c0_cause", "c0_epc", "c0_prid",
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"c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
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"c0_xcontext", "$21", "$22", "c0_debug",
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"c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
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"c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
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};
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/* XLR's CP0 Select Registers. */
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static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
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{ 9, 6, "c0_extintreq" },
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{ 9, 7, "c0_extintmask" },
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{ 15, 1, "c0_ebase" },
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{ 16, 1, "c0_config1" },
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{ 16, 2, "c0_config2" },
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{ 16, 3, "c0_config3" },
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{ 16, 7, "c0_procid2" },
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{ 18, 1, "c0_watchlo,1" },
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{ 18, 2, "c0_watchlo,2" },
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{ 18, 3, "c0_watchlo,3" },
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{ 18, 4, "c0_watchlo,4" },
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{ 18, 5, "c0_watchlo,5" },
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{ 18, 6, "c0_watchlo,6" },
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{ 18, 7, "c0_watchlo,7" },
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{ 19, 1, "c0_watchhi,1" },
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{ 19, 2, "c0_watchhi,2" },
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{ 19, 3, "c0_watchhi,3" },
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{ 19, 4, "c0_watchhi,4" },
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{ 19, 5, "c0_watchhi,5" },
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{ 19, 6, "c0_watchhi,6" },
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{ 19, 7, "c0_watchhi,7" },
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{ 25, 1, "c0_perfcnt,1" },
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{ 25, 2, "c0_perfcnt,2" },
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{ 25, 3, "c0_perfcnt,3" },
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{ 25, 4, "c0_perfcnt,4" },
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{ 25, 5, "c0_perfcnt,5" },
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{ 25, 6, "c0_perfcnt,6" },
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{ 25, 7, "c0_perfcnt,7" },
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{ 27, 1, "c0_cacheerr,1" },
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{ 27, 2, "c0_cacheerr,2" },
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{ 27, 3, "c0_cacheerr,3" },
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{ 28, 1, "c0_datalo" },
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{ 29, 1, "c0_datahi" }
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};
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static const char * const mips_hwr_names_numeric[32] =
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static const char * const mips_hwr_names_numeric[32] =
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{
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{
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"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
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"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
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"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
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"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
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"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
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"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
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| Line 407... |
Line 457... |
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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{ "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
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{ "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
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{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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{ "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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{ "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
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{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
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/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
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Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
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Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
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| Line 460... |
Line 514... |
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{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
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{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
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ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
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ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
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mips_hwr_names_numeric },
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mips_hwr_names_numeric },
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{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
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ISA_MIPS64 | INSN_XLR,
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mips_cp0_names_xlr,
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mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
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mips_hwr_names_numeric },
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/* This entry, mips16, is here only for ISA/processor selection; do
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/* This entry, mips16, is here only for ISA/processor selection; do
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not print its name. */
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not print its name. */
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{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
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{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
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};
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};
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| Line 880... |
Line 940... |
else
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else
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(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
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(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
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break;
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break;
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}
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}
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case 'x': /* bbit bit index */
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(*info->fprintf_func) (info->stream, "0x%lx",
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(l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
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break;
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case 'p': /* cins, cins32, exts and exts32 position */
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(*info->fprintf_func) (info->stream, "0x%lx",
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(l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
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break;
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case 's': /* cins and exts length-minus-one */
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(*info->fprintf_func) (info->stream, "0x%lx",
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(l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
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break;
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case 'S': /* cins32 and exts32 length-minus-one field */
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(*info->fprintf_func) (info->stream, "0x%lx",
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(l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
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break;
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case 'Q': /* seqi/snei immediate field */
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op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
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/* Sign-extend it. */
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op = (op ^ 512) - 512;
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(*info->fprintf_func) (info->stream, "%d", op);
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break;
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default:
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default:
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/* xgettext:c-format */
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/* xgettext:c-format */
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(*info->fprintf_func) (info->stream,
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(*info->fprintf_func) (info->stream,
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_("# internal error, undefined extension sequence (+%c)"),
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_("# internal error, undefined extension sequence (+%c)"),
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*d);
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*d);
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| Line 1075... |
Line 1162... |
case 'z':
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case 'z':
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(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
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(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
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break;
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break;
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case '<':
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case '<':
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case '1':
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(*info->fprintf_func) (info->stream, "0x%lx",
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(*info->fprintf_func) (info->stream, "0x%lx",
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(l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
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(l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
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break;
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break;
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case 'c':
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case 'c':
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| Line 2037... |
Line 2125... |
return print_insn_mips16 (memaddr, info);
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return print_insn_mips16 (memaddr, info);
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#endif
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#endif
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#if SYMTAB_AVAILABLE
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#if SYMTAB_AVAILABLE
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if (info->mach == bfd_mach_mips16
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if (info->mach == bfd_mach_mips16
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|| (info->flavour == bfd_target_elf_flavour
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|| (info->symbols != NULL
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&& info->symbols != NULL
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&& bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
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&& ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
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&& ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
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== STO_MIPS16)))
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->internal_elf_sym.st_other)))
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return print_insn_mips16 (memaddr, info);
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return print_insn_mips16 (memaddr, info);
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#endif
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#endif
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status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
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status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
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if (status == 0)
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if (status == 0)
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