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Steve Tjiang, John Newlin, and Scott Foehner.
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Steve Tjiang, John Newlin, and Scott Foehner.
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Michael Eager and staff of Xilinx, Inc., contributed support for the
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Michael Eager and staff of Xilinx, Inc., contributed support for the
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Xilinx MicroBlaze architecture.
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Xilinx MicroBlaze architecture.
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The original port to the OpenRISC 1000 is believed to be due to
|
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Alessandro Forin and Per Bothner. More recent ports have been the work
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of Jeremy Bennett.
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@node Sample Session
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@node Sample Session
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@chapter A Sample @value{GDBN} Session
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@chapter A Sample @value{GDBN} Session
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You can use this manual at your leisure to read all about @value{GDBN}.
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You can use this manual at your leisure to read all about @value{GDBN}.
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However, a handful of commands are enough to get started using the
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However, a handful of commands are enough to get started using the
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Line 18310... |
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@node OpenRISC 1000
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@node OpenRISC 1000
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@subsection OpenRISC 1000
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@subsection OpenRISC 1000
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@cindex OpenRISC 1000
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@cindex OpenRISC 1000
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@cindex or1k boards
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Previous versions of @value{GDBN} supported remote connection via a
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See OR1k Architecture document (@uref{www.opencores.org}) for more information
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proprietary JTAG protocol using the @samp{target jtag} command. Support
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about platform and commands.
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for this has now been dropped.
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@table @code
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@table @code
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@kindex target jtag
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@kindex target remote
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@item target jtag jtag://@var{host}:@var{port}
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@item target remote
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This is now the only way to connect to a remote OpenRISC 1000
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target. This is supported by @dfn{Or1ksim}, the OpenRISC 1000
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architectural simulator, and Verilator and Icarus Verilog
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simulations. @dfn{Remote serial protocol} servers are also available to
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drive various hardware implementations via JTAG.
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Connects to remote JTAG server.
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Connects to remote JTAG server.
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JTAG remote server can be either an or1ksim or JTAG server,
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connected via parallel port to the board.
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Example: @code{target jtag jtag://localhost:9999}
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Example: @code{target remote :51000}
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@kindex target sim
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@item target sim
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@kindex or1ksim
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@dfn{Or1ksim}, the OpenRISC 1000 architectural simulator is now
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@item or1ksim @var{command}
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incorporated within @value{GDBN} as a simulator target. It is started
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If connected to @code{or1ksim} OpenRISC 1000 Architectural
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in quiet mode with 8M of memory starting at address 0. It is possible
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Simulator, proprietary commands can be executed.
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to pass arguments to extend this configuration using the @samp{-f}
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option to @samp{target sim}. However for more complex use, the user is
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advised to run @dfn{Or1ksim} separately, with its own configuration
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file, and connect using @samp{target remote}
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@kindex info or1k spr
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Example: @code{target sim}
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@kindex info spr
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@item info or1k spr
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@item info or1k spr
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Displays spr groups.
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Displays groups.
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@item info or1k spr @var{group}
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@item info spr @var{group}
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@itemx info or1k spr @var{groupno}
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@itemx info spr @var{groupno}
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Displays register names in selected group.
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Displays register names in selected group.
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@item info or1k spr @var{group} @var{register}
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@item info spr @var{group} @var{register}
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@itemx info or1k spr @var{register}
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@itemx info spr @var{register}
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@itemx info or1k spr @var{groupno} @var{registerno}
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@itemx info spr @var{groupno} @var{registerno}
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@itemx info or1k spr @var{registerno}
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@itemx info spr @var{registerno}
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Shows information about specified spr register.
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Shows information about specified spr register.
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Example: @code{info spr DRR}
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@code{DEBUG.DRR = SPR6_21 = 0 (0x0)}
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@kindex spr
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@kindex spr
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@item spr @var{group} @var{register} @var{value}
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@item spr @var{group} @var{register} @var{value}
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@itemx spr @var{register @var{value}}
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@itemx spr @var{register @var{value}}
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@itemx spr @var{groupno} @var{registerno @var{value}}
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@itemx spr @var{groupno} @var{registerno @var{value}}
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@itemx spr @var{registerno @var{value}}
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@itemx spr @var{registerno @var{value}}
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Writes @var{value} to specified spr register.
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Writes @var{value} to specified spr register.
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@end table
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Some implementations of OpenRISC 1000 Architecture also have hardware trace.
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Example: spr PICMR 0x24
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It is very similar to @value{GDBN} trace, except it does not interfere with normal
|
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program execution and is thus much faster. Hardware breakpoints/watchpoint
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triggers can be set using:
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@table @code
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@item $LEA/$LDATA
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Load effective address/data
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@item $SEA/$SDATA
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Store effective address/data
|
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@item $AEA/$ADATA
|
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Access effective address ($SEA or $LEA) or data ($SDATA/$LDATA)
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|
@item $FETCH
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Fetch data
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@end table
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@end table
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When triggered, it can capture low level data, like: @code{PC}, @code{LSEA},
|
The use of @samp{info} and @samp{spr} commands is anachronistic. At
|
@code{LDATA}, @code{SDATA}, @code{READSPR}, @code{WRITESPR}, @code{INSTR}.
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some time in the future they will be replaced by @samp{show spr} and
|
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@samp{set spr}.
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@code{htrace} commands:
|
|
@cindex OpenRISC 1000 htrace
|
|
@table @code
|
|
@kindex hwatch
|
|
@item hwatch @var{conditional}
|
|
Set hardware watchpoint on combination of Load/Store Effective Address(es)
|
|
or Data. For example:
|
|
|
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@code{hwatch ($LEA == my_var) && ($LDATA < 50) || ($SEA == my_var) && ($SDATA >= 50)}
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|
|
|
@code{hwatch ($LEA == my_var) && ($LDATA < 50) || ($SEA == my_var) && ($SDATA >= 50)}
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|
|
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@kindex htrace
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There are some known problems with the current implementation
|
@item htrace info
|
@cindex OpenRISC 1000 known problems
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Display information about current HW trace configuration.
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|
|
|
@item htrace trigger @var{conditional}
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@enumerate
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Set starting criteria for HW trace.
|
|
|
|
@item htrace qualifier @var{conditional}
|
|
Set acquisition qualifier for HW trace.
|
|
|
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@item htrace stop @var{conditional}
|
|
Set HW trace stopping criteria.
|
|
|
|
@item htrace record [@var{data}]*
|
|
Selects the data to be recorded, when qualifier is met and HW trace was
|
|
triggered.
|
|
|
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@item htrace enable
|
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@itemx htrace disable
|
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Enables/disables the HW trace.
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|
|
|
@item htrace rewind [@var{filename}]
|
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Clears currently recorded trace data.
|
|
|
|
If filename is specified, new trace file is made and any newly collected data
|
|
will be written there.
|
|
|
|
@item htrace print [@var{start} [@var{len}]]
|
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Prints trace buffer, using current record configuration.
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|
|
|
@item htrace mode continuous
|
@item
|
Set continuous trace mode.
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@cindex OpenRISC 1000 known problems, hardware breakpoints and watchpoints
|
|
Some OpenRISC 1000 targets support hardware breakpoints and watchpoints.
|
|
Consult the target documentation for details. @value{GDBN} is not
|
|
perfect in handling of watchpoints. It is possible to allocate hardware
|
|
watchpoints and not discover until running that sufficient watchpoints
|
|
are not available. It is also possible that GDB will report watchpoints
|
|
being hit spuriously. This can be down to the assembly code having
|
|
additional memory accesses that are not obviously reflected in the
|
|
source code.
|
|
|
|
@item
|
|
@cindex OpenRISC 1000 known problems, architectural compatability
|
|
The OpenRISC 1000 architecture has evolved since the first port of @value{GDBN}. In particular the structure of the Unit Present register has
|
|
changed and the CPU Configuration register has been added. The port of
|
|
@value{GDBN} version @value{GDBVN} uses the @emph{current}
|
|
specification of the OpenRISC 1000.
|
|
|
@item htrace mode suspend
|
@end enumerate
|
Set suspend trace mode.
|
|
|
|
@end table
|
@cindex Bugs, reporting
|
|
@cindex Reporting bugs
|
|
Reports of bugs are much welcomed. Please report problems through the
|
|
OpenRISC tracker at @uref{http://opencores.org/openrisc,downloads}.
|
|
|
@node PowerPC Embedded
|
@node PowerPC Embedded
|
@subsection PowerPC Embedded
|
@subsection PowerPC Embedded
|
|
|
@cindex DVC register
|
@cindex DVC register
|
