| Line 362... |
Line 362... |
int len)
|
int len)
|
{
|
{
|
int res = or1ksim_read_mem (mem, buf, len);
|
int res = or1ksim_read_mem (mem, buf, len);
|
|
|
#ifdef OR32_SIM_DEBUG
|
#ifdef OR32_SIM_DEBUG
|
printf ("Reading %d bytes from 0x%8p\n", len, (void *) mem);
|
printf ("Reading %d bytes from %08p\n", len, (void *) mem);
|
#endif
|
#endif
|
|
|
return res;
|
return res;
|
|
|
} /* sim_read () */
|
} /* sim_read () */
|
| Line 388... |
Line 388... |
SIM_ADDR mem,
|
SIM_ADDR mem,
|
const unsigned char *buf,
|
const unsigned char *buf,
|
int len)
|
int len)
|
{
|
{
|
#ifdef OR32_SIM_DEBUG
|
#ifdef OR32_SIM_DEBUG
|
printf ("Writing %d bytes to 0x%8p\n", len, (void *) mem);
|
printf ("Writing %d bytes to %08p\n", len, (void *) mem);
|
#endif
|
#endif
|
|
|
return or1ksim_write_mem ((unsigned int) mem, buf, len);
|
return or1ksim_write_mem ((unsigned int) mem, buf, len);
|
|
|
} /* sim_write () */
|
} /* sim_write () */
|
| Line 427... |
Line 427... |
{
|
{
|
unsigned long int regval;
|
unsigned long int regval;
|
int res;
|
int res;
|
|
|
#ifdef OR32_SIM_DEBUG
|
#ifdef OR32_SIM_DEBUG
|
printf ("sim_fetch_register (regno=%d\n) called\n", regno);
|
printf ("sim_fetch_register (regno=%d) called\n", regno);
|
#endif
|
#endif
|
if (4 != len)
|
if (4 != len)
|
{
|
{
|
fprintf (stderr, "Invalid register length %d\n", len);
|
fprintf (stderr, "Invalid register length %d\n", len);
|
return 0;
|
return 0;
|
| Line 646... |
Line 646... |
resumption NPC must be set to the PPC to allow re-execution of the
|
resumption NPC must be set to the PPC to allow re-execution of the
|
trapped instruction. */
|
trapped instruction. */
|
switch (res)
|
switch (res)
|
{
|
{
|
case OR1KSIM_RC_HALTED:
|
case OR1KSIM_RC_HALTED:
|
|
|
|
#ifdef OR32_SIM_DEBUG
|
|
(void) or1ksim_read_reg (OR32_NPC_REGNUM, &npc);
|
|
printf (" execution halted at 0x%08lx.\n", npc);
|
|
#endif
|
|
|
sd->last_reason = sim_exited;
|
sd->last_reason = sim_exited;
|
(void) or1ksim_read_reg (OR32_FIRST_ARG_REGNUM, &retval);
|
(void) or1ksim_read_reg (OR32_FIRST_ARG_REGNUM, &retval);
|
sd->last_rc = (unsigned int) retval;
|
sd->last_rc = (unsigned int) retval;
|
sd->resume_npc = OR32_RESET_EXCEPTION;
|
sd->resume_npc = OR32_RESET_EXCEPTION;
|
cycles = (long int) (or1ksim_get_time_period ()
|
cycles = (long int) (or1ksim_get_time_period ()
|
* (double) or1ksim_clock_rate());
|
* (double) or1ksim_clock_rate());
|
break;
|
break;
|
|
|
case OR1KSIM_RC_BRKPT:
|
case OR1KSIM_RC_BRKPT:
|
|
|
|
#ifdef OR32_SIM_DEBUG
|
|
printf (" execution hit breakpoint.\n");
|
|
#endif
|
|
|
sd->last_reason = sim_stopped;
|
sd->last_reason = sim_stopped;
|
sd->last_rc = TARGET_SIGNAL_TRAP;
|
sd->last_rc = TARGET_SIGNAL_TRAP;
|
|
|
/* This could have been a breakpoint or single step. */
|
/* This could have been a breakpoint or single step. */
|
if (step)
|
if (step)
|
