URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.17.0/] [libgloss/] [or32/] [crt0.S] - Diff between revs 184 and 194

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Rev 184	Rev 194
Line 109...	Line 109...
`.section .vectors,"ax"`	`.section .vectors,"ax"`

`/* 0x100: RESET exception */`	`/* 0x100: RESET exception */`
`.org 0x100`	`.org 0x100`
`_reset:`	`_reset:`
`l.nop`

`/* Jump to program initialisation code */`	`/* Jump to program initialisation code */`
`l.movhi r2,hi(_start)`	`l.j _start`
`l.ori r2,r2,lo(_start)`
`l.jr r2`
`l.nop`	`l.nop`

`/* 0x200: BUS exception is special, because during startup we use it`	`/* 0x200: BUS exception is special, because during startup we use it`
`to detect where the stack should go. So we need some special code`	`to detect where the stack should go. So we need some special code`
`before we return, which wel will later overwrite with l.nop.`	`before we return, which wel will later overwrite with l.nop.`
Line 315...	Line 311...
`l.bf .L6`	`l.bf .L6`
`l.nop`	`l.nop`

`l.sw 0(r30),r26 /* Patch the instruction */`	`l.sw 0(r30),r26 /* Patch the instruction */`
`l.j .L5`	`l.j .L5`
`l.addi r30,r30,4 /* Next instruction */`	`l.addi r30,r30,4 /* Delay slot: next instruction */`

`.L6:`	`.L6:`
`/* Cache initialisation */`	`/* Cache initialisation. Enable IC and/or DC */`
`.if IC_ENABLE \|\| DC_ENABLE`	`.if IC_ENABLE \|\| DC_ENABLE`
`/* Flush IC and/or DC */`	`l.mfspr r10,r0,SPR_SR`
`l.addi r10,r0,0`
`l.addi r11,r0,0`
`l.addi r12,r0,0`
`.if IC_ENABLE`
`l.addi r11,r0,IC_SIZE`
`.endif`
`.if DC_ENABLE`
`l.addi r12,r0,DC_SIZE`
`.endif`
`l.sfleu r12,r11`
`l.bf .L0`
`l.nop`
`l.add r11,r0,r12`
`.L0:`
`.if IC_ENABLE`	`.if IC_ENABLE`
`l.mtspr r0,r10,SPR_ICBIR`	`l.ori r10,r10,SPR_SR_ICE`
`.endif`	`.endif`
`.if DC_ENABLE`	`.if DC_ENABLE`
`l.mtspr r0,r10,SPR_DCBIR`	`l.ori r10,r10,SPR_SR_DCE`
`.endif`
`l.sfne r10,r11`
`l.bf .L0`
`l.addi r10,r10,16`

`/* Enable IC and/or DC */`
`l.addi r10,r0,(SPR_SR_SM)`
`.if IC_ENABLE`
`l.ori r10,r10,(SPR_SR_ICE)`
`.endif`
`.if DC_ENABLE`
`l.ori r10,r10,(SPR_SR_DCE)`
`.endif`	`.endif`
`l.mtspr r0,r10,SPR_SR`	`l.mtspr r0,r10,SPR_SR`
`l.nop`	`l.nop /* Flush the pipeline. */`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`.endif`	`.endif`
Line 371...	Line 341...

`.L1:`	`.L1:`
`l.sw (0)(r28),r0`	`l.sw (0)(r28),r0`
`l.sfltu r28,r30`	`l.sfltu r28,r30`
`l.bf .L1`	`l.bf .L1`
`l.addi r28,r28,4`	`l.addi r28,r28,4 /* Delay slot */`

`/* Call global and static constructors */`	`/* Call global and static constructors */`
`l.movhi r3,hi(init)`	`l.jal init`
`l.ori r3,r3,lo(init)`	`l.nop`
`l.jalr r3`

`/* Set up destructors to be called from exit if main never returns */`	`/* Set up destructors to be called from exit if main never returns */`
`l.movhi r3,hi(fini)`	`l.movhi r3,hi(fini)`
`l.ori r3,r3,lo(fini)`
`l.jal _atexit`	`l.jal _atexit`
	`l.ori r3,r3,lo(fini) /* Delay slot */`

`/* Initialise UART in a C function. If the UART isn't present, we'll */`	`/* Initialise UART in a C function. If the UART isn't present, we'll */`
`/* link against a dummy function. */`	`/* link against a dummy function. */`
`l.jal __uart_init`	`l.jal __uart_init`
`l.nop`	`l.nop`

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[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.17.0/] [libgloss/] [or32/] [crt0.S] - Diff between revs 184 and 194