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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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Rev 226 |
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directory. */
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directory. */
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#ifndef OR1KSIM_BOARD__H
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#ifndef OR1KSIM_BOARD__H
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#define OR1KSIM_BOARD__H
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#define OR1KSIM_BOARD__H
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/* Cache information */
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/* Cache information (no longer used, cache configured through UPR and CCFGRs)*/
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#define IC_ENABLE 1
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#define IC_ENABLE 1
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#define IC_SIZE 4096
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#define IC_SIZE 8192
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#define DC_ENABLE 0
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#define DC_ENABLE 0
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#define DC_SIZE 8192
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#define DC_SIZE 8192
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#define SDRAM_BASE_ADDR 0x00000000
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#define SDRAM_BASE_ADDR 0x00000000
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