OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [or32/] [or1ksim-board.h] - Diff between revs 207 and 226

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 207 Rev 226
Line 29... Line 29...
   directory. */
   directory. */
 
 
#ifndef OR1KSIM_BOARD__H
#ifndef OR1KSIM_BOARD__H
#define OR1KSIM_BOARD__H
#define OR1KSIM_BOARD__H
 
 
/* Cache information */
/* Cache information (no longer used, cache configured through UPR and CCFGRs)*/
#define IC_ENABLE           1
#define IC_ENABLE           1
#define IC_SIZE          4096
#define IC_SIZE          8192
 
 
#define DC_ENABLE           0
#define DC_ENABLE           0
#define DC_SIZE          8192
#define DC_SIZE          8192
 
 
#define SDRAM_BASE_ADDR 0x00000000
#define SDRAM_BASE_ADDR 0x00000000

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.