URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [newlib-1.18.0/] [newlib/] [libc/] [machine/] [or32/] [or1k-support-asm.S] - Diff between revs 517 and 551

Rev 517	Rev 551
Line 215...	Line 215...
`*/`	`*/`
`/* -------------------------------------------------------------------------- */`	`/* -------------------------------------------------------------------------- */`
`.global or1k_icache_disable`	`.global or1k_icache_disable`
`.type or1k_icache_disable,@function`	`.type or1k_icache_disable,@function`

`or1k_icache_disble:`	`or1k_icache_disable:`
`/* Disable IC */`	`/* Disable IC */`
`l.mfspr r13,r0,SPR_SR`	`l.mfspr r13,r0,SPR_SR`
`l.addi r12,r0,-1`	`l.addi r12,r0,-1`
`l.xori r12,r12,SPR_SR_ICE`	`l.xori r12,r12,SPR_SR_ICE`
`l.and r12,r13,r12`	`l.and r12,r13,r12`
Line 265...	Line 265...
`*/`	`*/`
`/* -------------------------------------------------------------------------- */`	`/* -------------------------------------------------------------------------- */`
`.global or1k_dcache_disable`	`.global or1k_dcache_disable`
`.type or1k_dcache_disable,@function`	`.type or1k_dcache_disable,@function`

`or1k_dcache_disble:`	`or1k_dcache_disable:`
`/* Disable DC */`	`/* Disable DC */`
`l.mfspr r13,r0,SPR_SR`	`l.mfspr r13,r0,SPR_SR`
`l.addi r12,r0,-1`	`l.addi r12,r0,-1`
`l.xori r12,r12,SPR_SR_DCE`	`l.xori r12,r12,SPR_SR_DCE`
`l.and r12,r13,r12`	`l.and r12,r13,r12`