| Line 38... |
Line 38... |
supported instructions table.
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supported instructions table.
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v0.11 | 19/1/11 | Julius Baxter | Cache information update.
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v0.11 | 19/1/11 | Julius Baxter | Cache information update.
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Wishbone behavior clarification. Serial integer multiply/divide update.
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Wishbone behavior clarification. Serial integer multiply/divide update.
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Reset address clarification
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Reset address clarification
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v0.12 | 13/9/11 | Julius Baxter | Addition of extension instructions
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l.extbs, l.extbz, l.exths, l.exthz, l.extws and l.extwz. Range exception
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support, overflow bit in supervision register.
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__vend__
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__vend__
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////
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////
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|
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Introduction
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Introduction
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------------
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------------
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| Line 236... |
Line 240... |
- External interrupt request
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- External interrupt request
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- Certain memory access condition
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- Certain memory access condition
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- Internal errors, such as an attempt to execute unimplemented opcode
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- Internal errors, such as an attempt to execute unimplemented opcode
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- System call
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- System call
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- Internal exception, such as breakpoint exceptions
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- Internal exception, such as breakpoint exceptions
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- Arithmetic overflow
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|
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((Exception handling)) is transparent to user software and uses the same
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((Exception handling)) is transparent to user software and uses the same
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mechanism to handle all types of exceptions. When an exception is taken,
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mechanism to handle all types of exceptions. When an exception is taken,
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control is transferred to an exception handler at an offset defined by for
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control is transferred to an exception handler at an offset defined by for
|
the type of exception encountered. Exceptions are handled in supervisor mode.
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the type of exception encountered. Exceptions are handled in supervisor mode.
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| Line 591... |
Line 596... |
| ((l.and)) |
|
| ((l.and)) |
|
| ((l.andi)) |
|
| ((l.andi)) |
|
| ((l.bf)) |
|
| ((l.bf)) |
|
| ((l.bnf)) |
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| ((l.bnf)) |
|
| ((l.div)) | Yes
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| ((l.div)) | Yes
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|
| ((l.extbs)) | Yes
|
|
| ((l.extbz)) | Yes
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| ((l.exths)) | Yes
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| ((l.exthz)) | Yes
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| ((l.extws)) | Yes
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| ((l.extwz)) | Yes
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| ((l.ff1)) | Yes
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| ((l.ff1)) | Yes
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| ((l.fl1)) | Yes
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| ((l.fl1)) | Yes
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| ((l.j)) |
|
| ((l.j)) |
|
| ((l.jal)) |
|
| ((l.jal)) |
|
| ((l.jalr)) |
|
| ((l.jalr)) |
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| Line 782... |
Line 793... |
| Illegal Instruction | 0x700 | Illegal instruction in the instruction stream.
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| Illegal Instruction | 0x700 | Illegal instruction in the instruction stream.
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| High Priority External Interrupt | 0x800 | High priority external
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| High Priority External Interrupt | 0x800 | High priority external
|
interrupt asserted.
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interrupt asserted.
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| D-TLB Miss | 0x900 | No matching entry in DTLB (DTLB miss).
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| D-TLB Miss | 0x900 | No matching entry in DTLB (DTLB miss).
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| I-TLB Miss | 0xA00 | No matching entry in ITLB (ITLB miss).
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| I-TLB Miss | 0xA00 | No matching entry in ITLB (ITLB miss).
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| Range | 0xB00 | If programmed in the SR, the setting of SR[OV],
|
|
usually by an arithmetic instruction, causes a range exception.
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| System Call | 0xC00 | System call initiated by software.
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| System Call | 0xC00 | System call initiated by software.
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| Floating point exception | 0xD00 | FP operation caused flags in FPCSR to
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| Floating point exception | 0xD00 | FP operation caused flags in FPCSR to
|
become set.
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become set.
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| Trap | 0xE00 | Trap instruction was decoded
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| Trap | 0xE00 | Trap instruction was decoded
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|===========================================================
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|===========================================================
|
