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[/] [openrisc/] [trunk/] [or1200/] [doc/] [openrisc1200_spec.txt] - Diff between revs 645 and 647

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Rev 645 Rev 647
Line 38... Line 38...
supported instructions table.
supported instructions table.
 
 
v0.11   | 19/1/11       | Julius Baxter | Cache information update.
v0.11   | 19/1/11       | Julius Baxter | Cache information update.
Wishbone behavior clarification. Serial integer multiply/divide update.
Wishbone behavior clarification. Serial integer multiply/divide update.
Reset address clarification
Reset address clarification
 
 
 
v0.12   | 13/9/11       | Julius Baxter | Addition of extension instructions
 
l.extbs, l.extbz, l.exths, l.exthz, l.extws and l.extwz. Range exception
 
support, overflow bit in supervision register.
__vend__
__vend__
////
////
 
 
Introduction
Introduction
------------
------------
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- External interrupt request
- External interrupt request
- Certain memory access condition
- Certain memory access condition
- Internal errors, such as an attempt to execute unimplemented opcode
- Internal errors, such as an attempt to execute unimplemented opcode
- System call
- System call
- Internal exception, such as breakpoint exceptions
- Internal exception, such as breakpoint exceptions
 
- Arithmetic overflow
 
 
((Exception handling)) is transparent to user software and uses the same
((Exception handling)) is transparent to user software and uses the same
mechanism to handle all types of exceptions. When an exception is taken,
mechanism to handle all types of exceptions. When an exception is taken,
control is transferred to an exception handler at an offset defined by for
control is transferred to an exception handler at an offset defined by for
the type of exception encountered. Exceptions are handled in supervisor mode.
the type of exception encountered. Exceptions are handled in supervisor mode.
Line 591... Line 596...
| ((l.and))             |
| ((l.and))             |
| ((l.andi))            |
| ((l.andi))            |
| ((l.bf))              |
| ((l.bf))              |
| ((l.bnf))             |
| ((l.bnf))             |
| ((l.div))             | Yes
| ((l.div))             | Yes
 
| ((l.extbs))           | Yes
 
| ((l.extbz))           | Yes
 
| ((l.exths))           | Yes
 
| ((l.exthz))           | Yes
 
| ((l.extws))           | Yes
 
| ((l.extwz))           | Yes
| ((l.ff1))             | Yes
| ((l.ff1))             | Yes
| ((l.fl1))             | Yes
| ((l.fl1))             | Yes
| ((l.j))               |
| ((l.j))               |
| ((l.jal))             |
| ((l.jal))             |
| ((l.jalr))            |
| ((l.jalr))            |
Line 782... Line 793...
| Illegal Instruction   | 0x700 | Illegal instruction in the instruction stream.
| Illegal Instruction   | 0x700 | Illegal instruction in the instruction stream.
| High Priority External Interrupt      | 0x800 | High priority external
| High Priority External Interrupt      | 0x800 | High priority external
  interrupt asserted.
  interrupt asserted.
| D-TLB Miss    | 0x900 | No matching entry in DTLB (DTLB miss).
| D-TLB Miss    | 0x900 | No matching entry in DTLB (DTLB miss).
| I-TLB Miss    | 0xA00 | No matching entry in ITLB (ITLB miss).
| I-TLB Miss    | 0xA00 | No matching entry in ITLB (ITLB miss).
 
| Range         | 0xB00 | If programmed in the SR, the setting of  SR[OV],
 
  usually by an arithmetic instruction, causes a range exception.
| System Call   | 0xC00 | System call initiated by software.
| System Call   | 0xC00 | System call initiated by software.
| Floating point exception      | 0xD00 | FP operation caused flags in FPCSR to
| Floating point exception      | 0xD00 | FP operation caused flags in FPCSR to
  become set.
  become set.
| Trap  | 0xE00 | Trap instruction was decoded
| Trap  | 0xE00 | Trap instruction was decoded
|===========================================================
|===========================================================

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