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Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_alu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Defines added, flags are corrected.
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//
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// Revision 1.15 2005/01/07 09:23:39 andreje
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// l.ff1 and l.cmov instructions added
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//
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// Revision 1.14 2004/06/08 18:17:36 lampret
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// Revision 1.14 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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// Non-functional changes. Coding style fixes.
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//
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//
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// Revision 1.13 2004/05/09 19:49:03 lampret
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// Revision 1.13 2004/05/09 19:49:03 lampret
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// Added some l.cust5 custom instructions as example
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// Added some l.cust5 custom instructions as example
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| Line 165... |
Line 172... |
wire [width-1:0] result_csum;
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wire [width-1:0] result_csum;
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wire cy_csum;
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wire cy_csum;
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`endif
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`endif
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wire [width-1:0] result_and;
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wire [width-1:0] result_and;
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wire cy_sum;
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wire cy_sum;
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`ifdef OR1200_IMPL_SUB
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wire cy_sub;
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`endif
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reg cyforw;
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reg cyforw;
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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| Line 176... |
Line 186... |
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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assign a_eq_b = (comp_a == comp_b);
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assign a_eq_b = (comp_a == comp_b);
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assign a_lt_b = (comp_a < comp_b);
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assign a_lt_b = (comp_a < comp_b);
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`endif
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`endif
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`ifdef OR1200_IMPL_SUB
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assign cy_sub = a < b;
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`endif
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assign {cy_sum, result_sum} = a + b;
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assign {cy_sum, result_sum} = a + b;
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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assign {cy_csum, result_csum} = a + b + {32'd0, carry};
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assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
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`endif
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`endif
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assign result_and = a & b;
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assign result_and = a & b;
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//
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//
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// Simulation check for bad ALU behavior
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// Simulation check for bad ALU behavior
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| Line 197... |
Line 210... |
`endif
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`endif
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//
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//
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// Central part of the ALU
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// Central part of the ALU
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//
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//
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always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
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always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
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`ifdef OR1200_IMPL_ADDC
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or result_csum
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`endif
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) begin
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`ifdef OR1200_CASE_DEFAULT
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`ifdef OR1200_CASE_DEFAULT
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casex (alu_op) // synopsys parallel_case
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casex (alu_op) // synopsys parallel_case
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`else
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`else
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casex (alu_op) // synopsys full_case parallel_case
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casex (alu_op) // synopsys full_case parallel_case
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`endif
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`endif
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| Line 220... |
Line 237... |
`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADDC : begin
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`OR1200_ALUOP_ADDC : begin
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result = result_csum;
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result = result_csum;
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end
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end
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`endif
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`endif
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`ifdef OR1200_IMPL_SUB
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`OR1200_ALUOP_SUB : begin
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`OR1200_ALUOP_SUB : begin
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result = a - b;
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result = a - b;
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end
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end
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`endif
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`OR1200_ALUOP_XOR : begin
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`OR1200_ALUOP_XOR : begin
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result = a ^ b;
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result = a ^ b;
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end
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end
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`OR1200_ALUOP_OR : begin
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`OR1200_ALUOP_OR : begin
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result = a | b;
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result = a | b;
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| Line 256... |
Line 275... |
end
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end
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`ifdef OR1200_CASE_DEFAULT
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`ifdef OR1200_CASE_DEFAULT
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default: begin
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default: begin
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`else
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`else
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`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
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`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
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begin
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`endif
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`endif
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result=result_and;
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result=result_and;
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end
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end
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endcase
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endcase
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end
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end
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| Line 295... |
Line 313... |
end
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end
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//
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//
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// Generate flag and flag write enable
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// Generate flag and flag write enable
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//
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//
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always @(alu_op or result_sum or result_and or flagcomp) begin
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always @(alu_op or result_sum or result_and or flagcomp
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`ifdef OR1200_IMPL_ADDC
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or result_csum
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`endif
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) begin
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casex (alu_op) // synopsys parallel_case
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casex (alu_op) // synopsys parallel_case
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`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
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`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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flagforw = (result_sum == 32'h0000_0000);
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flagforw = (result_sum == 32'h0000_0000);
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flag_we = 1'b1;
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flag_we = 1'b1;
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| Line 318... |
Line 340... |
`OR1200_ALUOP_COMP: begin
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`OR1200_ALUOP_COMP: begin
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flagforw = flagcomp;
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flagforw = flagcomp;
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flag_we = 1'b1;
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flag_we = 1'b1;
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end
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end
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default: begin
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default: begin
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flagforw = 1'b0;
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flagforw = flagcomp;
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flag_we = 1'b0;
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flag_we = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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//
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//
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// Generate SR[CY] write enable
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// Generate SR[CY] write enable
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//
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//
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always @(alu_op or cy_sum
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always @(alu_op or cy_sum
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`ifdef OR1200_IMPL_CY
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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or cy_csum
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or cy_csum
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`endif
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`endif
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`ifdef OR1200_IMPL_SUB
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or cy_sub
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`endif
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`endif
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) begin
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) begin
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casex (alu_op) // synopsys parallel_case
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casex (alu_op) // synopsys parallel_case
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`ifdef OR1200_IMPL_CY
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`ifdef OR1200_IMPL_CY
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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cyforw = cy_sum;
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cyforw = cy_sum;
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| Line 344... |
Line 371... |
`OR1200_ALUOP_ADDC: begin
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`OR1200_ALUOP_ADDC: begin
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cyforw = cy_csum;
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cyforw = cy_csum;
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cy_we = 1'b1;
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cy_we = 1'b1;
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end
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end
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`endif
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`endif
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`ifdef OR1200_IMPL_SUB
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`OR1200_ALUOP_SUB: begin
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cyforw = cy_sub;
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cy_we = 1'b1;
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end
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`endif
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`endif
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`endif
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default: begin
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default: begin
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cyforw = 1'b0;
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cyforw = 1'b0;
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cy_we = 1'b0;
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cy_we = 1'b0;
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end
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end
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