OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Diff between revs 258 and 364

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 258 Rev 364
Line 146... Line 146...
`ifdef OR1200_IMPL_ADDC
`ifdef OR1200_IMPL_ADDC
         or result_csum
         or result_csum
`endif
`endif
) begin
) begin
`ifdef OR1200_CASE_DEFAULT
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op)          // synopsys parallel_case
        casez (alu_op)          // synopsys parallel_case
`else
`else
        casex (alu_op)          // synopsys full_case parallel_case
        casez (alu_op)          // synopsys full_case parallel_case
`endif
`endif
                `OR1200_ALUOP_FF1: begin
                `OR1200_ALUOP_FF1: begin
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
                end
                end
                `OR1200_ALUOP_CUST5 : begin
                `OR1200_ALUOP_CUST5 : begin
Line 218... Line 218...
// l.cust5 custom instructions
// l.cust5 custom instructions
//
//
// Examples for move byte, set bit and clear bit
// Examples for move byte, set bit and clear bit
//
//
always @(cust5_op or cust5_limm or a or b) begin
always @(cust5_op or cust5_limm or a or b) begin
        casex (cust5_op)                // synopsys parallel_case
        casez (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                5'h1 : begin
                        casex (cust5_limm[1:0])
                        casez (cust5_limm[1:0])
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                        endcase
Line 248... Line 248...
always @(alu_op or result_sum or result_and or flagcomp
always @(alu_op or result_sum or result_and or flagcomp
`ifdef OR1200_IMPL_ADDC
`ifdef OR1200_IMPL_ADDC
         or result_csum
         or result_csum
`endif
`endif
) begin
) begin
        casex (alu_op)          // synopsys parallel_case
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                        flag_we = 1'b1;
                end
                end
Line 289... Line 289...
`ifdef OR1200_IMPL_SUB
`ifdef OR1200_IMPL_SUB
        or cy_sub
        or cy_sub
`endif
`endif
`endif
`endif
) begin
) begin
        casex (alu_op)          // synopsys parallel_case
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                        cyforw = cy_sum;
                        cy_we = 1'b1;
                        cy_we = 1'b1;
                end
                end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.