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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Diff between revs 10 and 141

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Rev 10 Rev 141
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////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_alu.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Defines added, flags are corrected. 
 
//
 
// Revision 1.15  2005/01/07 09:23:39  andreje
 
// l.ff1 and l.cmov instructions added
 
//
// Revision 1.14  2004/06/08 18:17:36  lampret
// Revision 1.14  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
// Non-functional changes. Coding style fixes.
//
//
// Revision 1.13  2004/05/09 19:49:03  lampret
// Revision 1.13  2004/05/09 19:49:03  lampret
// Added some l.cust5 custom instructions as example
// Added some l.cust5 custom instructions as example
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wire    [width-1:0]              result_csum;
wire    [width-1:0]              result_csum;
wire                            cy_csum;
wire                            cy_csum;
`endif
`endif
wire    [width-1:0]              result_and;
wire    [width-1:0]              result_and;
wire                            cy_sum;
wire                            cy_sum;
 
`ifdef OR1200_IMPL_SUB
 
wire                            cy_sub;
 
`endif
reg                             cyforw;
reg                             cyforw;
 
 
//
//
// Combinatorial logic
// Combinatorial logic
//
//
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`endif
 
`ifdef OR1200_IMPL_SUB
 
assign cy_sub = a < b;
 
`endif
assign {cy_sum, result_sum} = a + b;
assign {cy_sum, result_sum} = a + b;
`ifdef OR1200_IMPL_ADDC
`ifdef OR1200_IMPL_ADDC
assign {cy_csum, result_csum} = a + b + {32'd0, carry};
assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
`endif
`endif
assign result_and = a & b;
assign result_and = a & b;
 
 
//
//
// Simulation check for bad ALU behavior
// Simulation check for bad ALU behavior
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`endif
`endif
 
 
//
//
// Central part of the ALU
// Central part of the ALU
//
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
 
`ifdef OR1200_IMPL_ADDC
 
         or result_csum
 
`endif
 
) begin
`ifdef OR1200_CASE_DEFAULT
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op)          // synopsys parallel_case
        casex (alu_op)          // synopsys parallel_case
`else
`else
        casex (alu_op)          // synopsys full_case parallel_case
        casex (alu_op)          // synopsys full_case parallel_case
`endif
`endif
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`ifdef OR1200_IMPL_ADDC
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                                result = result_csum;
                end
                end
`endif
`endif
 
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB : begin
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                                result = a - b;
                end
                end
 
`endif
                `OR1200_ALUOP_XOR : begin
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                                result = a ^ b;
                end
                end
                `OR1200_ALUOP_OR  : begin
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                                result = a | b;
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    end
    end
 
 
`ifdef OR1200_CASE_DEFAULT
`ifdef OR1200_CASE_DEFAULT
    default: begin
    default: begin
`else
`else
    `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
    begin
 
`endif
`endif
      result=result_and;
      result=result_and;
    end
    end
        endcase
        endcase
end
end
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end
end
 
 
//
//
// Generate flag and flag write enable
// Generate flag and flag write enable
//
//
always @(alu_op or result_sum or result_and or flagcomp) begin
always @(alu_op or result_sum or result_and or flagcomp
 
`ifdef OR1200_IMPL_ADDC
 
         or result_csum
 
`endif
 
) begin
        casex (alu_op)          // synopsys parallel_case
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                        flag_we = 1'b1;
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                `OR1200_ALUOP_COMP: begin
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                        flag_we = 1'b1;
                end
                end
                default: begin
                default: begin
                        flagforw = 1'b0;
                        flagforw = flagcomp;
                        flag_we = 1'b0;
                        flag_we = 1'b0;
                end
                end
        endcase
        endcase
end
end
 
 
//
//
// Generate SR[CY] write enable
// Generate SR[CY] write enable
//
//
always @(alu_op or cy_sum
always @(alu_op or cy_sum
 
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_ADDC
`ifdef OR1200_IMPL_ADDC
        or cy_csum
        or cy_csum
`endif
`endif
 
`ifdef OR1200_IMPL_SUB
 
        or cy_sub
 
`endif
 
`endif
        ) begin
        ) begin
        casex (alu_op)          // synopsys parallel_case
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                        cyforw = cy_sum;
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                `OR1200_ALUOP_ADDC: begin
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                        cyforw = cy_csum;
                        cy_we = 1'b1;
                        cy_we = 1'b1;
                end
                end
`endif
`endif
 
`ifdef OR1200_IMPL_SUB
 
                `OR1200_ALUOP_SUB: begin
 
                        cyforw = cy_sub;
 
                        cy_we = 1'b1;
 
                end
 
`endif
`endif
`endif
                default: begin
                default: begin
                        cyforw = 1'b0;
                        cyforw = 1'b0;
                        cy_we = 1'b0;
                        cy_we = 1'b0;
                end
                end

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