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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 10 |
Rev 141 |
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_cfgr.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// No update
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//
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// Revision 1.4 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.3 2002/03/29 15:16:54 lampret
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// Revision 1.3 2002/03/29 15:16:54 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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| Line 196... |
Line 202... |
// When configuration registers are not implemented, only
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// When configuration registers are not implemented, only
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// implement VR and UPR
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// implement VR and UPR
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//
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//
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always @(spr_addr)
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always @(spr_addr)
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`ifdef OR1200_SYS_FULL_DECODE
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`ifdef OR1200_SYS_FULL_DECODE
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if (!spr_addr[31:4])
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if (spr_addr[31:4] == 28'h0)
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`endif
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`endif
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case(spr_addr[3:0])
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case(spr_addr[3:0])
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`OR1200_SPRGRP_SYS_VR: begin
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`OR1200_SPRGRP_SYS_VR: begin
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spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV;
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spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV;
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spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1;
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spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1;
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