| Line 42... |
Line 42... |
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: or1200_cpu.v,v $
|
|
// Revision 2.0 2010/06/30 11:00:00 ORSoC
|
|
// Major update:
|
|
// Structure reordered and bugs fixed.
|
|
//
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// Revision 1.16 2005/01/07 09:28:37 andreje
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|
// flag for l.cmov instruction added
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|
//
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// Revision 1.15 2004/05/09 19:49:04 lampret
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// Revision 1.15 2004/05/09 19:49:04 lampret
|
// Added some l.cust5 custom instructions as example
|
// Added some l.cust5 custom instructions as example
|
//
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//
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// Revision 1.14 2004/04/05 08:29:57 lampret
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// Revision 1.14 2004/04/05 08:29:57 lampret
|
// Merged branch_qmem into main tree.
|
// Merged branch_qmem into main tree.
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| Line 157... |
Line 164... |
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
|
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
|
icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
|
icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
|
immu_en,
|
immu_en,
|
|
|
// Debug unit
|
// Debug unit
|
ex_insn, ex_freeze, id_pc, branch_op,
|
id_void, id_insn, ex_void,
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spr_dat_npc, rf_dataw,
|
ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
|
du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt,
|
spr_dat_npc, rf_dataw, ex_flushpipe,
|
du_except, du_dat_cpu,
|
du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop, du_except_trig,
|
|
du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu, du_lsu_store_dat, du_lsu_load_dat,
|
|
abort_mvspr, abort_ex,
|
|
|
// Data interface
|
// Data interface
|
dc_en,
|
dc_en,
|
dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
|
dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
|
dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
|
dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
|
dmmu_en,
|
sb_en, dmmu_en,
|
|
|
|
// SR Interface
|
|
boot_adr_sel_i,
|
|
|
// Interrupt & tick exceptions
|
// Interrupt & tick exceptions
|
sig_int, sig_tick,
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sig_int, sig_tick,
|
|
|
// SPR interface
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// SPR interface
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| Line 212... |
Line 224... |
output immu_en;
|
output immu_en;
|
|
|
//
|
//
|
// Debug interface
|
// Debug interface
|
//
|
//
|
|
output id_void;
|
|
output [31:0] id_insn;
|
|
output ex_void;
|
output [31:0] ex_insn;
|
output [31:0] ex_insn;
|
output ex_freeze;
|
output ex_freeze;
|
|
output [31:0] wb_insn;
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|
output wb_freeze;
|
output [31:0] id_pc;
|
output [31:0] id_pc;
|
|
output [31:0] ex_pc;
|
|
output [31:0] wb_pc;
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|
output ex_flushpipe;
|
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
|
|
input du_stall;
|
input du_stall;
|
input [dw-1:0] du_addr;
|
input [dw-1:0] du_addr;
|
input [dw-1:0] du_dat_du;
|
input [dw-1:0] du_dat_du;
|
input du_read;
|
input du_read;
|
input du_write;
|
input du_write;
|
input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
|
input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
|
|
input [24:0] du_dmr1;
|
input du_hwbkpt;
|
input du_hwbkpt;
|
output [12:0] du_except;
|
input du_hwbkpt_ls_r;
|
|
output [12:0] du_except_trig;
|
|
output [12:0] du_except_stop;
|
output [dw-1:0] du_dat_cpu;
|
output [dw-1:0] du_dat_cpu;
|
output [dw-1:0] rf_dataw;
|
output [dw-1:0] rf_dataw;
|
|
output [dw-1:0] du_lsu_store_dat;
|
|
output [dw-1:0] du_lsu_load_dat;
|
|
|
//
|
//
|
// Data (DC) interface
|
// Data (DC) interface
|
//
|
//
|
output [31:0] dcpu_adr_o;
|
output [31:0] dcpu_adr_o;
|
| Line 247... |
Line 272... |
output dc_en;
|
output dc_en;
|
|
|
//
|
//
|
// Data (DMMU) interface
|
// Data (DMMU) interface
|
//
|
//
|
|
output sb_en;
|
output dmmu_en;
|
output dmmu_en;
|
|
output abort_ex;
|
|
output abort_mvspr;
|
|
|
|
//
|
|
// SR Interface
|
|
//
|
|
input boot_adr_sel_i;
|
|
|
//
|
//
|
// SPR interface
|
// SPR interface
|
//
|
//
|
output supv;
|
output supv;
|
| Line 275... |
Line 308... |
|
|
//
|
//
|
// Internal wires
|
// Internal wires
|
//
|
//
|
wire [31:0] if_insn;
|
wire [31:0] if_insn;
|
|
wire saving_if_insn;
|
wire [31:0] if_pc;
|
wire [31:0] if_pc;
|
wire [31:2] lr_sav;
|
|
wire [aw-1:0] rf_addrw;
|
wire [aw-1:0] rf_addrw;
|
wire [aw-1:0] rf_addra;
|
wire [aw-1:0] rf_addra;
|
wire [aw-1:0] rf_addrb;
|
wire [aw-1:0] rf_addrb;
|
wire rf_rda;
|
wire rf_rda;
|
wire rf_rdb;
|
wire rf_rdb;
|
wire [dw-1:0] simm;
|
wire [dw-1:0] id_simm;
|
wire [dw-1:2] branch_addrofs;
|
wire [dw-1:2] id_branch_addrtarget;
|
|
wire [dw-1:2] ex_branch_addrtarget;
|
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op;
|
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op;
|
wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
|
wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
|
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
|
wire [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
|
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
|
wire [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
|
wire genpc_freeze;
|
wire genpc_freeze;
|
wire if_freeze;
|
wire if_freeze;
|
wire id_freeze;
|
wire id_freeze;
|
wire ex_freeze;
|
wire ex_freeze;
|
wire wb_freeze;
|
wire wb_freeze;
|
| Line 300... |
Line 335... |
wire [`OR1200_SEL_WIDTH-1:0] sel_b;
|
wire [`OR1200_SEL_WIDTH-1:0] sel_b;
|
wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
|
wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
|
wire [dw-1:0] rf_dataw;
|
wire [dw-1:0] rf_dataw;
|
wire [dw-1:0] rf_dataa;
|
wire [dw-1:0] rf_dataa;
|
wire [dw-1:0] rf_datab;
|
wire [dw-1:0] rf_datab;
|
|
wire [dw-1:0] muxed_a;
|
wire [dw-1:0] muxed_b;
|
wire [dw-1:0] muxed_b;
|
wire [dw-1:0] wb_forw;
|
wire [dw-1:0] wb_forw;
|
wire wbforw_valid;
|
wire wbforw_valid;
|
wire [dw-1:0] operand_a;
|
wire [dw-1:0] operand_a;
|
wire [dw-1:0] operand_b;
|
wire [dw-1:0] operand_b;
|
wire [dw-1:0] alu_dataout;
|
wire [dw-1:0] alu_dataout;
|
wire [dw-1:0] lsu_dataout;
|
wire [dw-1:0] lsu_dataout;
|
wire [dw-1:0] sprs_dataout;
|
wire [dw-1:0] sprs_dataout;
|
wire [31:0] lsu_addrofs;
|
wire [31:0] ex_simm;
|
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
|
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
|
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
wire [4:0] cust5_op;
|
wire [4:0] cust5_op;
|
wire [5:0] cust5_limm;
|
wire [5:0] cust5_limm;
|
wire flushpipe;
|
wire if_flushpipe;
|
|
wire id_flushpipe;
|
|
wire ex_flushpipe;
|
|
wire wb_flushpipe;
|
wire extend_flush;
|
wire extend_flush;
|
wire branch_taken;
|
wire ex_branch_taken;
|
wire flag;
|
wire flag;
|
wire flagforw;
|
wire flagforw;
|
wire flag_we;
|
wire flag_we;
|
|
wire flag_we_alu;
|
wire carry;
|
wire carry;
|
wire cyforw;
|
wire cyforw;
|
wire cy_we;
|
wire cy_we_alu;
|
|
wire cy_we_rf;
|
wire lsu_stall;
|
wire lsu_stall;
|
wire epcr_we;
|
wire epcr_we;
|
wire eear_we;
|
wire eear_we;
|
wire esr_we;
|
wire esr_we;
|
wire pc_we;
|
wire pc_we;
|
| Line 333... |
Line 374... |
wire [31:0] eear;
|
wire [31:0] eear;
|
wire [`OR1200_SR_WIDTH-1:0] esr;
|
wire [`OR1200_SR_WIDTH-1:0] esr;
|
wire sr_we;
|
wire sr_we;
|
wire [`OR1200_SR_WIDTH-1:0] to_sr;
|
wire [`OR1200_SR_WIDTH-1:0] to_sr;
|
wire [`OR1200_SR_WIDTH-1:0] sr;
|
wire [`OR1200_SR_WIDTH-1:0] sr;
|
|
wire except_flushpipe;
|
wire except_start;
|
wire except_start;
|
wire except_started;
|
wire except_started;
|
wire [31:0] wb_insn;
|
wire [31:0] wb_insn;
|
wire [15:0] spr_addrimm;
|
|
wire sig_syscall;
|
wire sig_syscall;
|
wire sig_trap;
|
wire sig_trap;
|
wire [31:0] spr_dat_cfgr;
|
wire [31:0] spr_dat_cfgr;
|
wire [31:0] spr_dat_rf;
|
wire [31:0] spr_dat_rf;
|
wire [31:0] spr_dat_npc;
|
wire [31:0] spr_dat_npc;
|
wire [31:0] spr_dat_ppc;
|
wire [31:0] spr_dat_ppc;
|
wire [31:0] spr_dat_mac;
|
wire [31:0] spr_dat_mac;
|
wire force_dslot_fetch;
|
wire force_dslot_fetch;
|
wire no_more_dslot;
|
wire no_more_dslot;
|
wire ex_void;
|
wire ex_void;
|
|
wire ex_spr_read;
|
|
wire ex_spr_write;
|
wire if_stall;
|
wire if_stall;
|
wire id_macrc_op;
|
wire id_macrc_op;
|
wire ex_macrc_op;
|
wire ex_macrc_op;
|
|
wire [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
|
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
|
wire [31:0] mult_mac_result;
|
wire [31:0] mult_mac_result;
|
wire mac_stall;
|
wire mac_stall;
|
|
wire [12:0] except_trig;
|
wire [12:0] except_stop;
|
wire [12:0] except_stop;
|
wire genpc_refetch;
|
wire genpc_refetch;
|
wire rfe;
|
wire rfe;
|
wire lsu_unstall;
|
wire lsu_unstall;
|
wire except_align;
|
wire except_align;
|
| Line 366... |
Line 411... |
wire except_itlbmiss;
|
wire except_itlbmiss;
|
wire except_immufault;
|
wire except_immufault;
|
wire except_ibuserr;
|
wire except_ibuserr;
|
wire except_dbuserr;
|
wire except_dbuserr;
|
wire abort_ex;
|
wire abort_ex;
|
|
wire abort_mvspr;
|
|
|
//
|
//
|
// Send exceptions to Debug Unit
|
// Send exceptions to Debug Unit
|
//
|
//
|
assign du_except = except_stop;
|
assign du_except_trig = except_trig;
|
|
assign du_except_stop = except_stop;
|
|
assign du_lsu_store_dat = operand_b;
|
|
assign du_lsu_load_dat = lsu_dataout;
|
|
|
//
|
//
|
// Data cache enable
|
// Data cache enable
|
//
|
//
|
|
`ifdef OR1200_NO_DC
|
|
assign dc_en = 1'b0;
|
|
`else
|
assign dc_en = sr[`OR1200_SR_DCE];
|
assign dc_en = sr[`OR1200_SR_DCE];
|
|
`endif
|
|
|
//
|
//
|
// Instruction cache enable
|
// Instruction cache enable
|
//
|
//
|
|
`ifdef OR1200_NO_IC
|
|
assign ic_en = 1'b0;
|
|
`else
|
assign ic_en = sr[`OR1200_SR_ICE];
|
assign ic_en = sr[`OR1200_SR_ICE];
|
|
`endif
|
|
|
|
//
|
|
// SB enable
|
|
//
|
|
`ifdef OR1200_SB_IMPLEMENTED
|
|
//assign sb_en = sr[`OR1200_SR_SBE]; // SBE not defined -- jb
|
|
`else
|
|
assign sb_en = 1'b0;
|
|
`endif
|
|
|
//
|
//
|
// DMMU enable
|
// DMMU enable
|
//
|
//
|
|
`ifdef OR1200_NO_DMMU
|
|
assign dmmu_en = 1'b0;
|
|
`else
|
assign dmmu_en = sr[`OR1200_SR_DME];
|
assign dmmu_en = sr[`OR1200_SR_DME];
|
|
`endif
|
|
|
//
|
//
|
// IMMU enable
|
// IMMU enable
|
//
|
//
|
assign immu_en = sr[`OR1200_SR_IME];
|
`ifdef OR1200_NO_IMMU
|
|
assign immu_en = 1'b0;
|
|
`else
|
|
assign immu_en = sr[`OR1200_SR_IME] & ~except_started;
|
|
`endif
|
|
|
//
|
//
|
// SUPV bit
|
// SUPV bit
|
//
|
//
|
assign supv = sr[`OR1200_SR_SM];
|
assign supv = sr[`OR1200_SR_SM];
|
|
|
//
|
//
|
|
// FLAG write enable
|
|
//
|
|
assign flag_we = flag_we_alu && ~abort_mvspr;
|
|
|
|
//
|
// Instantiation of instruction fetch block
|
// Instantiation of instruction fetch block
|
//
|
//
|
or1200_genpc or1200_genpc(
|
or1200_genpc or1200_genpc(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
| Line 410... |
Line 489... |
.icpu_sel_o(icpu_sel_o),
|
.icpu_sel_o(icpu_sel_o),
|
.icpu_tag_o(icpu_tag_o),
|
.icpu_tag_o(icpu_tag_o),
|
.icpu_rty_i(icpu_rty_i),
|
.icpu_rty_i(icpu_rty_i),
|
.icpu_adr_i(icpu_adr_i),
|
.icpu_adr_i(icpu_adr_i),
|
|
|
|
.pre_branch_op(pre_branch_op),
|
.branch_op(branch_op),
|
.branch_op(branch_op),
|
.except_type(except_type),
|
.except_type(except_type),
|
.except_start(except_start),
|
.except_start(except_start),
|
.except_prefix(sr[`OR1200_SR_EPH]),
|
.except_prefix(sr[`OR1200_SR_EPH]),
|
.branch_addrofs(branch_addrofs),
|
.id_branch_addrtarget(id_branch_addrtarget),
|
.lr_restor(operand_b),
|
.ex_branch_addrtarget(ex_branch_addrtarget),
|
|
.muxed_b(muxed_b),
|
|
.operand_b(operand_b),
|
.flag(flag),
|
.flag(flag),
|
.taken(branch_taken),
|
.flagforw(flagforw),
|
.binsn_addr(lr_sav),
|
.ex_branch_taken(ex_branch_taken),
|
.epcr(epcr),
|
.epcr(epcr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_pc_we(pc_we),
|
.spr_pc_we(pc_we),
|
.genpc_refetch(genpc_refetch),
|
.genpc_refetch(genpc_refetch),
|
.genpc_freeze(genpc_freeze),
|
.genpc_freeze(genpc_freeze),
|
.genpc_stop_prefetch(1'b0),
|
|
.no_more_dslot(no_more_dslot)
|
.no_more_dslot(no_more_dslot)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of instruction fetch block
|
// Instantiation of instruction fetch block
|
| Line 443... |
Line 524... |
.icpu_tag_i(icpu_tag_i),
|
.icpu_tag_i(icpu_tag_i),
|
|
|
.if_freeze(if_freeze),
|
.if_freeze(if_freeze),
|
.if_insn(if_insn),
|
.if_insn(if_insn),
|
.if_pc(if_pc),
|
.if_pc(if_pc),
|
.flushpipe(flushpipe),
|
.saving_if_insn(saving_if_insn),
|
|
.if_flushpipe(if_flushpipe),
|
.if_stall(if_stall),
|
.if_stall(if_stall),
|
.no_more_dslot(no_more_dslot),
|
.no_more_dslot(no_more_dslot),
|
.genpc_refetch(genpc_refetch),
|
.genpc_refetch(genpc_refetch),
|
.rfe(rfe),
|
.rfe(rfe),
|
.except_itlbmiss(except_itlbmiss),
|
.except_itlbmiss(except_itlbmiss),
|
| Line 462... |
Line 544... |
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.flushpipe(flushpipe),
|
.if_flushpipe(if_flushpipe),
|
|
.id_flushpipe(id_flushpipe),
|
|
.ex_flushpipe(ex_flushpipe),
|
|
.wb_flushpipe(wb_flushpipe),
|
|
.extend_flush(extend_flush),
|
|
.except_flushpipe(except_flushpipe),
|
|
.abort_mvspr(abort_mvspr),
|
.if_insn(if_insn),
|
.if_insn(if_insn),
|
|
.id_insn(id_insn),
|
.ex_insn(ex_insn),
|
.ex_insn(ex_insn),
|
.branch_op(branch_op),
|
.id_branch_op(pre_branch_op),
|
.branch_taken(branch_taken),
|
.ex_branch_op(branch_op),
|
|
.ex_branch_taken(ex_branch_taken),
|
.rf_addra(rf_addra),
|
.rf_addra(rf_addra),
|
.rf_addrb(rf_addrb),
|
.rf_addrb(rf_addrb),
|
.rf_rda(rf_rda),
|
.rf_rda(rf_rda),
|
.rf_rdb(rf_rdb),
|
.rf_rdb(rf_rdb),
|
.alu_op(alu_op),
|
.alu_op(alu_op),
|
.mac_op(mac_op),
|
.mac_op(mac_op),
|
.shrot_op(shrot_op),
|
.shrot_op(shrot_op),
|
.comp_op(comp_op),
|
.comp_op(comp_op),
|
.rf_addrw(rf_addrw),
|
.rf_addrw(rf_addrw),
|
.rfwb_op(rfwb_op),
|
.rfwb_op(rfwb_op),
|
|
.pc_we(pc_we),
|
.wb_insn(wb_insn),
|
.wb_insn(wb_insn),
|
.simm(simm),
|
.id_simm(id_simm),
|
.branch_addrofs(branch_addrofs),
|
.id_branch_addrtarget(id_branch_addrtarget),
|
.lsu_addrofs(lsu_addrofs),
|
.ex_branch_addrtarget(ex_branch_addrtarget),
|
|
.ex_simm(ex_simm),
|
.sel_a(sel_a),
|
.sel_a(sel_a),
|
.sel_b(sel_b),
|
.sel_b(sel_b),
|
.lsu_op(lsu_op),
|
.id_lsu_op(id_lsu_op),
|
.cust5_op(cust5_op),
|
.cust5_op(cust5_op),
|
.cust5_limm(cust5_limm),
|
.cust5_limm(cust5_limm),
|
|
.id_pc(id_pc),
|
|
.ex_pc(ex_pc),
|
.multicycle(multicycle),
|
.multicycle(multicycle),
|
.spr_addrimm(spr_addrimm),
|
|
.wbforw_valid(wbforw_valid),
|
.wbforw_valid(wbforw_valid),
|
.sig_syscall(sig_syscall),
|
.sig_syscall(sig_syscall),
|
.sig_trap(sig_trap),
|
.sig_trap(sig_trap),
|
.force_dslot_fetch(force_dslot_fetch),
|
.force_dslot_fetch(force_dslot_fetch),
|
.no_more_dslot(no_more_dslot),
|
.no_more_dslot(no_more_dslot),
|
|
.id_void(id_void),
|
.ex_void(ex_void),
|
.ex_void(ex_void),
|
|
.ex_spr_read(ex_spr_read),
|
|
.ex_spr_write(ex_spr_write),
|
|
.id_mac_op(id_mac_op),
|
.id_macrc_op(id_macrc_op),
|
.id_macrc_op(id_macrc_op),
|
.ex_macrc_op(ex_macrc_op),
|
.ex_macrc_op(ex_macrc_op),
|
.rfe(rfe),
|
.rfe(rfe),
|
.du_hwbkpt(du_hwbkpt),
|
.du_hwbkpt(du_hwbkpt),
|
.except_illegal(except_illegal)
|
.except_illegal(except_illegal)
|
| Line 507... |
Line 604... |
// Instantiation of register file
|
// Instantiation of register file
|
//
|
//
|
or1200_rf or1200_rf(
|
or1200_rf or1200_rf(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
|
.cy_we_i(cy_we_alu),
|
|
.cy_we_o(cy_we_rf),
|
.supv(sr[`OR1200_SR_SM]),
|
.supv(sr[`OR1200_SR_SM]),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.addrw(rf_addrw),
|
.addrw(rf_addrw),
|
.dataw(rf_dataw),
|
.dataw(rf_dataw),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.we(rfwb_op[0]),
|
.we(rfwb_op[0]),
|
.flushpipe(flushpipe),
|
.flushpipe(wb_flushpipe),
|
.addra(rf_addra),
|
.addra(rf_addra),
|
.rda(rf_rda),
|
.rda(rf_rda),
|
.dataa(rf_dataa),
|
.dataa(rf_dataa),
|
.addrb(rf_addrb),
|
.addrb(rf_addrb),
|
.rdb(rf_rdb),
|
.rdb(rf_rdb),
|
| Line 539... |
Line 638... |
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.rf_dataa(rf_dataa),
|
.rf_dataa(rf_dataa),
|
.rf_datab(rf_datab),
|
.rf_datab(rf_datab),
|
.ex_forw(rf_dataw),
|
.ex_forw(rf_dataw),
|
.wb_forw(wb_forw),
|
.wb_forw(wb_forw),
|
.simm(simm),
|
.simm(id_simm),
|
.sel_a(sel_a),
|
.sel_a(sel_a),
|
.sel_b(sel_b),
|
.sel_b(sel_b),
|
.operand_a(operand_a),
|
.operand_a(operand_a),
|
.operand_b(operand_b),
|
.operand_b(operand_b),
|
|
.muxed_a(muxed_a),
|
.muxed_b(muxed_b)
|
.muxed_b(muxed_b)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of CPU's ALU
|
// Instantiation of CPU's ALU
|
| Line 562... |
Line 662... |
.comp_op(comp_op),
|
.comp_op(comp_op),
|
.cust5_op(cust5_op),
|
.cust5_op(cust5_op),
|
.cust5_limm(cust5_limm),
|
.cust5_limm(cust5_limm),
|
.result(alu_dataout),
|
.result(alu_dataout),
|
.flagforw(flagforw),
|
.flagforw(flagforw),
|
.flag_we(flag_we),
|
.flag_we(flag_we_alu),
|
.cyforw(cyforw),
|
.cyforw(cyforw),
|
.cy_we(cy_we),
|
.cy_we(cy_we_alu),
|
.flag(flag),
|
.flag(flag),
|
.carry(carry)
|
.carry(carry)
|
);
|
);
|
|
|
//
|
//
|
| Line 598... |
Line 698... |
//
|
//
|
or1200_sprs or1200_sprs(
|
or1200_sprs or1200_sprs(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.addrbase(operand_a),
|
.addrbase(operand_a),
|
.addrofs(spr_addrimm),
|
.addrofs(ex_simm[15:0]),
|
.dat_i(operand_b),
|
.dat_i(operand_b),
|
.alu_op(alu_op),
|
.ex_spr_read(ex_spr_read),
|
|
.ex_spr_write(ex_spr_write),
|
.flagforw(flagforw),
|
.flagforw(flagforw),
|
.flag_we(flag_we),
|
.flag_we(flag_we),
|
.flag(flag),
|
.flag(flag),
|
.cyforw(cyforw),
|
.cyforw(cyforw),
|
.cy_we(cy_we),
|
.cy_we(cy_we_rf),
|
.carry(carry),
|
.carry(carry),
|
.to_wbmux(sprs_dataout),
|
.to_wbmux(sprs_dataout),
|
|
|
.du_addr(du_addr),
|
.du_addr(du_addr),
|
.du_dat_du(du_dat_du),
|
.du_dat_du(du_dat_du),
|
.du_read(du_read),
|
.du_read(du_read),
|
.du_write(du_write),
|
.du_write(du_write),
|
.du_dat_cpu(du_dat_cpu),
|
.du_dat_cpu(du_dat_cpu),
|
|
.boot_adr_sel_i(boot_adr_sel_i),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_pic(spr_dat_pic),
|
.spr_dat_pic(spr_dat_pic),
|
.spr_dat_tt(spr_dat_tt),
|
.spr_dat_tt(spr_dat_tt),
|
.spr_dat_pm(spr_dat_pm),
|
.spr_dat_pm(spr_dat_pm),
|
.spr_dat_cfgr(spr_dat_cfgr),
|
.spr_dat_cfgr(spr_dat_cfgr),
|
| Line 650... |
Line 751... |
|
|
//
|
//
|
// Instantiation of load/store unit
|
// Instantiation of load/store unit
|
//
|
//
|
or1200_lsu or1200_lsu(
|
or1200_lsu or1200_lsu(
|
.addrbase(operand_a),
|
.clk(clk),
|
.addrofs(lsu_addrofs),
|
.rst(rst),
|
.lsu_op(lsu_op),
|
.id_addrbase(muxed_a),
|
|
.id_addrofs(id_simm),
|
|
.ex_addrbase(operand_a),
|
|
.ex_addrofs(ex_simm),
|
|
.id_lsu_op(id_lsu_op),
|
.lsu_datain(operand_b),
|
.lsu_datain(operand_b),
|
.lsu_dataout(lsu_dataout),
|
.lsu_dataout(lsu_dataout),
|
.lsu_stall(lsu_stall),
|
.lsu_stall(lsu_stall),
|
.lsu_unstall(lsu_unstall),
|
.lsu_unstall(lsu_unstall),
|
.du_stall(du_stall),
|
.du_stall(du_stall),
|
.except_align(except_align),
|
.except_align(except_align),
|
.except_dtlbmiss(except_dtlbmiss),
|
.except_dtlbmiss(except_dtlbmiss),
|
.except_dmmufault(except_dmmufault),
|
.except_dmmufault(except_dmmufault),
|
.except_dbuserr(except_dbuserr),
|
.except_dbuserr(except_dbuserr),
|
|
.id_freeze(id_freeze),
|
|
.ex_freeze(ex_freeze),
|
|
.flushpipe(ex_flushpipe),
|
|
|
.dcpu_adr_o(dcpu_adr_o),
|
.dcpu_adr_o(dcpu_adr_o),
|
.dcpu_cycstb_o(dcpu_cycstb_o),
|
.dcpu_cycstb_o(dcpu_cycstb_o),
|
.dcpu_we_o(dcpu_we_o),
|
.dcpu_we_o(dcpu_we_o),
|
.dcpu_sel_o(dcpu_sel_o),
|
.dcpu_sel_o(dcpu_sel_o),
|
| Line 687... |
Line 795... |
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.rfwb_op(rfwb_op),
|
.rfwb_op(rfwb_op),
|
.muxin_a(alu_dataout),
|
.muxin_a(alu_dataout),
|
.muxin_b(lsu_dataout),
|
.muxin_b(lsu_dataout),
|
.muxin_c(sprs_dataout),
|
.muxin_c(sprs_dataout),
|
.muxin_d({lr_sav, 2'b0}),
|
.muxin_d(ex_pc),
|
.muxout(rf_dataw),
|
.muxout(rf_dataw),
|
.muxreg(wb_forw),
|
.muxreg(wb_forw),
|
.muxreg_valid(wbforw_valid)
|
.muxreg_valid(wbforw_valid)
|
);
|
);
|
|
|
| Line 700... |
Line 808... |
//
|
//
|
or1200_freeze or1200_freeze(
|
or1200_freeze or1200_freeze(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.multicycle(multicycle),
|
.multicycle(multicycle),
|
.flushpipe(flushpipe),
|
.flushpipe(wb_flushpipe),
|
.extend_flush(extend_flush),
|
.extend_flush(extend_flush),
|
.lsu_stall(lsu_stall),
|
.lsu_stall(lsu_stall),
|
.if_stall(if_stall),
|
.if_stall(if_stall),
|
.lsu_unstall(lsu_unstall),
|
.lsu_unstall(lsu_unstall),
|
.force_dslot_fetch(force_dslot_fetch),
|
.force_dslot_fetch(force_dslot_fetch),
|
.abort_ex(abort_ex),
|
.abort_ex(abort_ex),
|
.du_stall(du_stall),
|
.du_stall(du_stall),
|
.mac_stall(mac_stall),
|
.mac_stall(mac_stall),
|
|
.saving_if_insn(saving_if_insn),
|
.genpc_freeze(genpc_freeze),
|
.genpc_freeze(genpc_freeze),
|
.if_freeze(if_freeze),
|
.if_freeze(if_freeze),
|
.id_freeze(id_freeze),
|
.id_freeze(id_freeze),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
| Line 737... |
Line 846... |
.sig_syscall(sig_syscall),
|
.sig_syscall(sig_syscall),
|
.sig_trap(sig_trap),
|
.sig_trap(sig_trap),
|
.sig_itlbmiss(except_itlbmiss),
|
.sig_itlbmiss(except_itlbmiss),
|
.sig_immufault(except_immufault),
|
.sig_immufault(except_immufault),
|
.sig_tick(sig_tick),
|
.sig_tick(sig_tick),
|
.branch_taken(branch_taken),
|
.ex_branch_taken(ex_branch_taken),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_ack_i(icpu_ack_i),
|
.icpu_err_i(icpu_err_i),
|
.icpu_err_i(icpu_err_i),
|
.dcpu_ack_i(dcpu_ack_i),
|
.dcpu_ack_i(dcpu_ack_i),
|
.dcpu_err_i(dcpu_err_i),
|
.dcpu_err_i(dcpu_err_i),
|
.genpc_freeze(genpc_freeze),
|
.genpc_freeze(genpc_freeze),
|
| Line 749... |
Line 858... |
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.wb_freeze(wb_freeze),
|
.wb_freeze(wb_freeze),
|
.if_stall(if_stall),
|
.if_stall(if_stall),
|
.if_pc(if_pc),
|
.if_pc(if_pc),
|
.id_pc(id_pc),
|
.id_pc(id_pc),
|
.lr_sav(lr_sav),
|
.ex_pc(ex_pc),
|
.flushpipe(flushpipe),
|
.wb_pc(wb_pc),
|
|
.id_flushpipe(id_flushpipe),
|
|
.ex_flushpipe(ex_flushpipe),
|
.extend_flush(extend_flush),
|
.extend_flush(extend_flush),
|
|
.except_flushpipe(except_flushpipe),
|
|
.abort_mvspr(abort_mvspr),
|
.except_type(except_type),
|
.except_type(except_type),
|
.except_start(except_start),
|
.except_start(except_start),
|
.except_started(except_started),
|
.except_started(except_started),
|
.except_stop(except_stop),
|
.except_stop(except_stop),
|
|
.except_trig(except_trig),
|
.ex_void(ex_void),
|
.ex_void(ex_void),
|
.spr_dat_ppc(spr_dat_ppc),
|
.spr_dat_ppc(spr_dat_ppc),
|
.spr_dat_npc(spr_dat_npc),
|
.spr_dat_npc(spr_dat_npc),
|
|
|
.datain(operand_b),
|
.datain(spr_dat_cpu),
|
|
.branch_op(branch_op),
|
.du_dsr(du_dsr),
|
.du_dsr(du_dsr),
|
|
.du_dmr1(du_dmr1),
|
|
.du_hwbkpt(du_hwbkpt),
|
|
.du_hwbkpt_ls_r(du_hwbkpt_ls_r),
|
.epcr_we(epcr_we),
|
.epcr_we(epcr_we),
|
.eear_we(eear_we),
|
.eear_we(eear_we),
|
.esr_we(esr_we),
|
.esr_we(esr_we),
|
.pc_we(pc_we),
|
.pc_we(pc_we),
|
.epcr(epcr),
|
.epcr(epcr),
|
