URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Diff between revs 642 and 808

Rev 642	Rev 808
Line 287...	Line 287...
wire [`OR1200_FPCSR_WIDTH-1:0] fpcsr;	wire [`OR1200_FPCSR_WIDTH-1:0] fpcsr;
`wire fpcsr_we;`	`wire fpcsr_we;`
`wire sr_we;`	`wire sr_we;`
wire [`OR1200_SR_WIDTH-1:0] to_sr;	wire [`OR1200_SR_WIDTH-1:0] to_sr;
wire [`OR1200_SR_WIDTH-1:0] sr;	wire [`OR1200_SR_WIDTH-1:0] sr;
	`wire dsx;`
`wire except_flushpipe;`	`wire except_flushpipe;`
`wire except_start;`	`wire except_start;`
`wire except_started;`	`wire except_started;`
`wire fpu_except_started;`	`wire fpu_except_started;`
`wire [31:0] wb_insn;`	`wire [31:0] wb_insn;`
Line 721...	Line 722...
`.spr_dat_fpu(spr_dat_fpu),`	`.spr_dat_fpu(spr_dat_fpu),`

`.sr_we(sr_we),`	`.sr_we(sr_we),`
`.to_sr(to_sr),`	`.to_sr(to_sr),`
`.sr(sr),`	`.sr(sr),`
`.branch_op(branch_op)`	`.branch_op(branch_op),`
	`.dsx(dsx)`
`);`	`);`

`//`	`//`
`// Instantiation of load/store unit`	`// Instantiation of load/store unit`
`//`	`//`
Line 875...	Line 877...

`.lsu_addr(dcpu_adr_o),`	`.lsu_addr(dcpu_adr_o),`
`.sr_we(sr_we),`	`.sr_we(sr_we),`
`.to_sr(to_sr),`	`.to_sr(to_sr),`
`.sr(sr),`	`.sr(sr),`
`.abort_ex(abort_ex)`	`.abort_ex(abort_ex),`
	`.dsx(dsx)`
`);`	`);`

`//`	`//`
`// Instantiation of configuration registers`	`// Instantiation of configuration registers`
`//`	`//`