| Line 64... |
Line 64... |
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// Debug unit
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// Debug unit
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id_void, id_insn, ex_void,
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id_void, id_insn, ex_void,
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ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
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ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
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spr_dat_npc, rf_dataw, ex_flushpipe,
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spr_dat_npc, rf_dataw, ex_flushpipe,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop, du_except_trig,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop,
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du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu, du_lsu_store_dat, du_lsu_load_dat,
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du_except_trig, du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu,
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du_lsu_store_dat, du_lsu_load_dat,
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abort_mvspr, abort_ex,
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abort_mvspr, abort_ex,
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// Data interface
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// Data interface
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dc_en,
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dc_en,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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dcpu_dat_o, dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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sb_en, dmmu_en,
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sb_en, dmmu_en, dc_no_writethrough,
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// SR Interface
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// SR Interface
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boot_adr_sel_i,
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boot_adr_sel_i,
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// Interrupt & tick exceptions
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// Interrupt & tick exceptions
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sig_int, sig_tick,
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sig_int, sig_tick,
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// SPR interface
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// SPR interface
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supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
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supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
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spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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| Line 165... |
Line 166... |
input dcpu_ack_i;
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input dcpu_ack_i;
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input dcpu_rty_i;
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input dcpu_rty_i;
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input dcpu_err_i;
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input dcpu_err_i;
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input [3:0] dcpu_tag_i;
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input [3:0] dcpu_tag_i;
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output dc_en;
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output dc_en;
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output dc_no_writethrough;
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//
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//
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// Data (DMMU) interface
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// Data (DMMU) interface
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//
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//
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output sb_en;
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output sb_en;
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| Line 194... |
Line 196... |
output [dw-1:0] spr_addr;
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output [dw-1:0] spr_addr;
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output [dw-1:0] spr_dat_cpu;
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output [dw-1:0] spr_dat_cpu;
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output [dw-1:0] spr_dat_npc;
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output [dw-1:0] spr_dat_npc;
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output [31:0] spr_cs;
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output [31:0] spr_cs;
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output spr_we;
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output spr_we;
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input mtspr_dc_done;
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//
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//
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// Interrupt exceptions
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// Interrupt exceptions
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//
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//
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input sig_int;
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input sig_int;
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| Line 243... |
Line 246... |
wire [dw-1:0] operand_b;
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wire [dw-1:0] operand_b;
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wire [dw-1:0] alu_dataout;
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wire [dw-1:0] alu_dataout;
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wire [dw-1:0] lsu_dataout;
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wire [dw-1:0] lsu_dataout;
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wire [dw-1:0] sprs_dataout;
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wire [dw-1:0] sprs_dataout;
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wire [dw-1:0] fpu_dataout;
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wire [dw-1:0] fpu_dataout;
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wire fpu_done;
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wire [31:0] ex_simm;
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wire [31:0] ex_simm;
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wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
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wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
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wire [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
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wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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wire [4:0] cust5_op;
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wire [4:0] cust5_op;
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wire [5:0] cust5_limm;
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wire [5:0] cust5_limm;
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wire if_flushpipe;
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wire if_flushpipe;
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wire id_flushpipe;
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wire id_flushpipe;
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| Line 292... |
Line 297... |
wire [31:0] spr_dat_rf;
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wire [31:0] spr_dat_rf;
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wire [31:0] spr_dat_npc;
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wire [31:0] spr_dat_npc;
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wire [31:0] spr_dat_ppc;
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wire [31:0] spr_dat_ppc;
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wire [31:0] spr_dat_mac;
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wire [31:0] spr_dat_mac;
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wire [31:0] spr_dat_fpu;
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wire [31:0] spr_dat_fpu;
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wire mtspr_done;
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wire force_dslot_fetch;
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wire force_dslot_fetch;
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wire no_more_dslot;
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wire no_more_dslot;
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wire ex_void;
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wire ex_void;
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wire ex_spr_read;
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wire ex_spr_read;
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wire ex_spr_write;
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wire ex_spr_write;
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| Line 385... |
Line 391... |
//
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//
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assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
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assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
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assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
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assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
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//
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//
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// Flag for any MTSPR instructions, that must block execution, to indicate done
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//
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assign mtspr_done = mtspr_dc_done;
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//
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// Instantiation of instruction fetch block
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// Instantiation of instruction fetch block
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//
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//
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or1200_genpc or1200_genpc(
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or1200_genpc or1200_genpc(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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| Line 490... |
Line 502... |
.cust5_op(cust5_op),
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.cust5_op(cust5_op),
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.cust5_limm(cust5_limm),
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.cust5_limm(cust5_limm),
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.id_pc(id_pc),
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.id_pc(id_pc),
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.ex_pc(ex_pc),
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.ex_pc(ex_pc),
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.multicycle(multicycle),
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.multicycle(multicycle),
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.wait_on(wait_on),
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.wbforw_valid(wbforw_valid),
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.wbforw_valid(wbforw_valid),
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.sig_syscall(sig_syscall),
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.sig_syscall(sig_syscall),
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.sig_trap(sig_trap),
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.sig_trap(sig_trap),
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.force_dslot_fetch(force_dslot_fetch),
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.force_dslot_fetch(force_dslot_fetch),
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.no_more_dslot(no_more_dslot),
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.no_more_dslot(no_more_dslot),
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| Line 504... |
Line 517... |
.id_mac_op(id_mac_op),
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.id_mac_op(id_mac_op),
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.id_macrc_op(id_macrc_op),
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.id_macrc_op(id_macrc_op),
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.ex_macrc_op(ex_macrc_op),
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.ex_macrc_op(ex_macrc_op),
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.rfe(rfe),
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.rfe(rfe),
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.du_hwbkpt(du_hwbkpt),
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.du_hwbkpt(du_hwbkpt),
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.except_illegal(except_illegal)
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.except_illegal(except_illegal),
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.dc_no_writethrough(dc_no_writethrough)
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);
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);
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//
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//
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// Instantiation of register file
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// Instantiation of register file
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//
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//
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| Line 532... |
Line 546... |
.datab(rf_datab),
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.datab(rf_datab),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
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.spr_write(spr_we),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_o(spr_dat_rf)
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.spr_dat_o(spr_dat_rf),
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.du_read(du_read)
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);
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);
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//
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//
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// Instantiation of operand muxes
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// Instantiation of operand muxes
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//
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//
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| Line 595... |
Line 610... |
.ex_freeze(ex_freeze),
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.ex_freeze(ex_freeze),
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.a(operand_a),
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.a(operand_a),
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.b(operand_b),
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.b(operand_b),
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.fpu_op(fpu_op),
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.fpu_op(fpu_op),
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.result(fpu_dataout),
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.result(fpu_dataout),
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.done(fpu_done),
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.flagforw(flagforw_fpu),
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.flagforw(flagforw_fpu),
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.flag_we(flag_we_fpu),
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.flag_we(flag_we_fpu),
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.sig_fp(sig_fp),
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.sig_fp(sig_fp),
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.except_started(fpu_except_started),
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.except_started(fpu_except_started),
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.fpcsr_we(fpcsr_we),
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.fpcsr_we(fpcsr_we),
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| Line 753... |
Line 769... |
//
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//
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or1200_freeze or1200_freeze(
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or1200_freeze or1200_freeze(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.multicycle(multicycle),
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.multicycle(multicycle),
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.wait_on(wait_on),
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.fpu_done(fpu_done),
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.mtspr_done(mtspr_done),
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.flushpipe(wb_flushpipe),
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.flushpipe(wb_flushpipe),
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.extend_flush(extend_flush),
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.extend_flush(extend_flush),
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.lsu_stall(lsu_stall),
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.lsu_stall(lsu_stall),
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.if_stall(if_stall),
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.if_stall(if_stall),
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.lsu_unstall(lsu_unstall),
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.lsu_unstall(lsu_unstall),
|
