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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Diff between revs 186 and 258

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Rev 186 Rev 258
Line 64... Line 64...
 
 
        // Debug unit
        // Debug unit
        id_void, id_insn, ex_void,
        id_void, id_insn, ex_void,
        ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
        ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
        spr_dat_npc, rf_dataw, ex_flushpipe,
        spr_dat_npc, rf_dataw, ex_flushpipe,
        du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop, du_except_trig,
        du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop,
        du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu, du_lsu_store_dat, du_lsu_load_dat,
        du_except_trig, du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu,
 
        du_lsu_store_dat, du_lsu_load_dat,
        abort_mvspr, abort_ex,
        abort_mvspr, abort_ex,
 
 
        // Data interface
        // Data interface
        dc_en,
        dc_en,
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o,
        dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
        dcpu_dat_o, dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
        sb_en, dmmu_en,
        sb_en, dmmu_en, dc_no_writethrough,
 
 
        // SR Interface
        // SR Interface
        boot_adr_sel_i,
        boot_adr_sel_i,
 
 
        // Interrupt & tick exceptions
        // Interrupt & tick exceptions
        sig_int, sig_tick,
        sig_int, sig_tick,
 
 
        // SPR interface
        // SPR interface
        supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
        supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done
);
);
 
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
 
 
Line 165... Line 166...
input                           dcpu_ack_i;
input                           dcpu_ack_i;
input                           dcpu_rty_i;
input                           dcpu_rty_i;
input                           dcpu_err_i;
input                           dcpu_err_i;
input   [3:0]                    dcpu_tag_i;
input   [3:0]                    dcpu_tag_i;
output                          dc_en;
output                          dc_en;
 
output                          dc_no_writethrough;
 
 
//
//
// Data (DMMU) interface
// Data (DMMU) interface
//
//
output                          sb_en;
output                          sb_en;
Line 194... Line 196...
output  [dw-1:0]         spr_addr;
output  [dw-1:0]         spr_addr;
output  [dw-1:0]         spr_dat_cpu;
output  [dw-1:0]         spr_dat_cpu;
output  [dw-1:0]         spr_dat_npc;
output  [dw-1:0]         spr_dat_npc;
output  [31:0]                   spr_cs;
output  [31:0]                   spr_cs;
output                          spr_we;
output                          spr_we;
 
input                           mtspr_dc_done;
 
 
//
//
// Interrupt exceptions
// Interrupt exceptions
//
//
input                           sig_int;
input                           sig_int;
Line 243... Line 246...
wire    [dw-1:0]         operand_b;
wire    [dw-1:0]         operand_b;
wire    [dw-1:0]         alu_dataout;
wire    [dw-1:0]         alu_dataout;
wire    [dw-1:0]         lsu_dataout;
wire    [dw-1:0]         lsu_dataout;
wire    [dw-1:0]         sprs_dataout;
wire    [dw-1:0]         sprs_dataout;
wire    [dw-1:0]         fpu_dataout;
wire    [dw-1:0]         fpu_dataout;
 
wire                            fpu_done;
wire    [31:0]                   ex_simm;
wire    [31:0]                   ex_simm;
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
 
wire    [`OR1200_WAIT_ON_WIDTH-1:0]      wait_on;
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
wire    [4:0]                    cust5_op;
wire    [4:0]                    cust5_op;
wire    [5:0]                    cust5_limm;
wire    [5:0]                    cust5_limm;
wire                            if_flushpipe;
wire                            if_flushpipe;
wire                            id_flushpipe;
wire                            id_flushpipe;
Line 292... Line 297...
wire    [31:0]                   spr_dat_rf;
wire    [31:0]                   spr_dat_rf;
wire    [31:0]                  spr_dat_npc;
wire    [31:0]                  spr_dat_npc;
wire    [31:0]                   spr_dat_ppc;
wire    [31:0]                   spr_dat_ppc;
wire    [31:0]                   spr_dat_mac;
wire    [31:0]                   spr_dat_mac;
wire [31:0]                      spr_dat_fpu;
wire [31:0]                      spr_dat_fpu;
 
wire                            mtspr_done;
wire                            force_dslot_fetch;
wire                            force_dslot_fetch;
wire                            no_more_dslot;
wire                            no_more_dslot;
wire                            ex_void;
wire                            ex_void;
wire                            ex_spr_read;
wire                            ex_spr_read;
wire                            ex_spr_write;
wire                            ex_spr_write;
Line 385... Line 391...
//
//
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
 
 
//
//
 
//  Flag for any MTSPR instructions, that must block execution, to indicate done
 
//
 
assign mtspr_done = mtspr_dc_done;
 
 
 
 
 
//
// Instantiation of instruction fetch block
// Instantiation of instruction fetch block
//
//
or1200_genpc or1200_genpc(
or1200_genpc or1200_genpc(
        .clk(clk),
        .clk(clk),
        .rst(rst),
        .rst(rst),
Line 490... Line 502...
        .cust5_op(cust5_op),
        .cust5_op(cust5_op),
        .cust5_limm(cust5_limm),
        .cust5_limm(cust5_limm),
        .id_pc(id_pc),
        .id_pc(id_pc),
        .ex_pc(ex_pc),
        .ex_pc(ex_pc),
        .multicycle(multicycle),
        .multicycle(multicycle),
 
        .wait_on(wait_on),
        .wbforw_valid(wbforw_valid),
        .wbforw_valid(wbforw_valid),
        .sig_syscall(sig_syscall),
        .sig_syscall(sig_syscall),
        .sig_trap(sig_trap),
        .sig_trap(sig_trap),
        .force_dslot_fetch(force_dslot_fetch),
        .force_dslot_fetch(force_dslot_fetch),
        .no_more_dslot(no_more_dslot),
        .no_more_dslot(no_more_dslot),
Line 504... Line 517...
        .id_mac_op(id_mac_op),
        .id_mac_op(id_mac_op),
        .id_macrc_op(id_macrc_op),
        .id_macrc_op(id_macrc_op),
        .ex_macrc_op(ex_macrc_op),
        .ex_macrc_op(ex_macrc_op),
        .rfe(rfe),
        .rfe(rfe),
        .du_hwbkpt(du_hwbkpt),
        .du_hwbkpt(du_hwbkpt),
        .except_illegal(except_illegal)
        .except_illegal(except_illegal),
 
        .dc_no_writethrough(dc_no_writethrough)
);
);
 
 
//
//
// Instantiation of register file
// Instantiation of register file
//
//
Line 532... Line 546...
        .datab(rf_datab),
        .datab(rf_datab),
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
        .spr_write(spr_we),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_rf)
        .spr_dat_o(spr_dat_rf),
 
        .du_read(du_read)
);
);
 
 
//
//
// Instantiation of operand muxes
// Instantiation of operand muxes
//
//
Line 595... Line 610...
        .ex_freeze(ex_freeze),
        .ex_freeze(ex_freeze),
        .a(operand_a),
        .a(operand_a),
        .b(operand_b),
        .b(operand_b),
        .fpu_op(fpu_op),
        .fpu_op(fpu_op),
        .result(fpu_dataout),
        .result(fpu_dataout),
 
        .done(fpu_done),
        .flagforw(flagforw_fpu),
        .flagforw(flagforw_fpu),
        .flag_we(flag_we_fpu),
        .flag_we(flag_we_fpu),
        .sig_fp(sig_fp),
        .sig_fp(sig_fp),
        .except_started(fpu_except_started),
        .except_started(fpu_except_started),
        .fpcsr_we(fpcsr_we),
        .fpcsr_we(fpcsr_we),
Line 753... Line 769...
//
//
or1200_freeze or1200_freeze(
or1200_freeze or1200_freeze(
        .clk(clk),
        .clk(clk),
        .rst(rst),
        .rst(rst),
        .multicycle(multicycle),
        .multicycle(multicycle),
 
        .wait_on(wait_on),
 
        .fpu_done(fpu_done),
 
        .mtspr_done(mtspr_done),
        .flushpipe(wb_flushpipe),
        .flushpipe(wb_flushpipe),
        .extend_flush(extend_flush),
        .extend_flush(extend_flush),
        .lsu_stall(lsu_stall),
        .lsu_stall(lsu_stall),
        .if_stall(if_stall),
        .if_stall(if_stall),
        .lsu_unstall(lsu_unstall),
        .lsu_unstall(lsu_unstall),

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