| Line 41... |
Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_ctrl.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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//
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// Revision 1.13 2005/01/13 11:03:43 phoenix
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// revert to the old l.sfxxi behavior
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//
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// Revision 1.12 2005/01/07 09:31:07 andreje
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// Revision 1.12 2005/01/07 09:31:07 andreje
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// sign/zero extension for l.sfxxi instructions corrected
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// sign/zero extension for l.sfxxi instructions corrected
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//
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//
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// Revision 1.11 2004/06/08 18:17:36 lampret
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// Revision 1.11 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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// Non-functional changes. Coding style fixes.
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| Line 126... |
Line 133... |
module or1200_ctrl(
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module or1200_ctrl(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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|
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// Internal i/f
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// Internal i/f
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id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op, branch_taken,
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except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe, wb_flushpipe,
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id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
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id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
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rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
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rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
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wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
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wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a, sel_b, id_lsu_op,
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cust5_op, cust5_limm,
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cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
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multicycle, spr_addrimm, wbforw_valid, du_hwbkpt, sig_syscall, sig_trap,
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multicycle, wbforw_valid, sig_syscall, sig_trap,
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force_dslot_fetch, no_more_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal
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force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read, ex_spr_write,
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id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
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input ex_freeze;
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input wb_freeze;
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input wb_freeze;
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input flushpipe;
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output if_flushpipe;
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output id_flushpipe;
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output ex_flushpipe;
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output wb_flushpipe;
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input extend_flush;
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input except_flushpipe;
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input abort_mvspr ;
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input [31:0] if_insn;
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input [31:0] if_insn;
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output [31:0] id_insn;
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output [31:0] ex_insn;
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output [31:0] ex_insn;
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output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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output [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
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input branch_taken;
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output [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
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input ex_branch_taken;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
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output rf_rda;
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output rf_rda;
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output rf_rdb;
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output rf_rdb;
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output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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output [`OR1200_MACOP_WIDTH-1:0] mac_op;
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output [`OR1200_MACOP_WIDTH-1:0] mac_op;
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output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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input pc_we;
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output [31:0] wb_insn;
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output [31:0] wb_insn;
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output [31:0] simm;
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output [31:2] id_branch_addrtarget;
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output [31:2] branch_addrofs;
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output [31:2] ex_branch_addrtarget;
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output [31:0] lsu_addrofs;
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output [`OR1200_SEL_WIDTH-1:0] sel_a;
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output [`OR1200_SEL_WIDTH-1:0] sel_a;
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output [`OR1200_SEL_WIDTH-1:0] sel_b;
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output [`OR1200_SEL_WIDTH-1:0] sel_b;
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output [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
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output [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
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output [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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output [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
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output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
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output [4:0] cust5_op;
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output [4:0] cust5_op;
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output [5:0] cust5_limm;
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output [5:0] cust5_limm;
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output [15:0] spr_addrimm;
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input [31:0] id_pc;
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input [31:0] ex_pc;
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output [31:0] id_simm;
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output [31:0] ex_simm;
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input wbforw_valid;
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input wbforw_valid;
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input du_hwbkpt;
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input du_hwbkpt;
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output sig_syscall;
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output sig_syscall;
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output sig_trap;
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output sig_trap;
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output force_dslot_fetch;
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output force_dslot_fetch;
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output no_more_dslot;
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output no_more_dslot;
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output id_void;
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output ex_void;
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output ex_void;
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output ex_spr_read;
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output ex_spr_write;
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output [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
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output id_macrc_op;
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output id_macrc_op;
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output ex_macrc_op;
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output ex_macrc_op;
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output rfe;
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output rfe;
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output except_illegal;
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output except_illegal;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
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reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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wire if_maci_op;
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`ifdef OR1200_MAC_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op;
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reg [`OR1200_MACOP_WIDTH-1:0] ex_mac_op;
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reg [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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reg ex_macrc_op;
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reg ex_macrc_op;
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`else
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`else
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire ex_macrc_op;
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wire ex_macrc_op;
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`endif
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`endif
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| Line 200... |
Line 228... |
reg [31:0] ex_insn;
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reg [31:0] ex_insn;
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reg [31:0] wb_insn;
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reg [31:0] wb_insn;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
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reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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reg [31:0] lsu_addrofs;
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reg [`OR1200_SEL_WIDTH-1:0] sel_a;
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reg [`OR1200_SEL_WIDTH-1:0] sel_a;
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reg [`OR1200_SEL_WIDTH-1:0] sel_b;
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reg [`OR1200_SEL_WIDTH-1:0] sel_b;
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reg sel_imm;
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reg sel_imm;
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reg [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
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reg [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
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reg [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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reg [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
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reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
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reg imm_signextend;
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reg [31:0] id_simm;
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reg [15:0] spr_addrimm;
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reg [31:0] ex_simm;
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reg sig_syscall;
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reg sig_syscall;
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reg sig_trap;
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reg sig_trap;
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reg except_illegal;
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reg except_illegal;
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wire id_void;
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wire id_void;
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wire ex_void;
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wire wb_void;
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reg ex_delayslot_dsi;
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reg ex_delayslot_nop;
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reg spr_read;
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reg spr_write;
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reg [31:2] ex_branch_addrtarget;
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//
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//
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// Register file read addresses
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// Register file read addresses
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//
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//
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assign rf_addra = if_insn[20:16];
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assign rf_addra = if_insn[20:16];
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assign rf_addrb = if_insn[15:11];
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assign rf_addrb = if_insn[15:11];
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assign rf_rda = if_insn[31];
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assign rf_rda = if_insn[31] || if_maci_op;
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assign rf_rdb = if_insn[30];
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assign rf_rdb = if_insn[30];
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//
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//
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// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
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// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
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// instructions
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// instructions
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//
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//
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// SIMON
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// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
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assign force_dslot_fetch = 1'b0;
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assign force_dslot_fetch = 1'b0;
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assign no_more_dslot = |branch_op & !id_void & branch_taken | (branch_op == `OR1200_BRANCHOP_RFE);
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assign no_more_dslot = (|ex_branch_op & !id_void & ex_branch_taken) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
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assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
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assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
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assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
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assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
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assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
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assign ex_spr_write = spr_write && !abort_mvspr;
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assign ex_spr_read = spr_read && !abort_mvspr;
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//
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//
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// Sign/Zero extension of immediates
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// ex_delayslot_dsi: delay slot insn is in EX stage
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// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops jump/branch was executed)
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//
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//
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assign simm = (imm_signextend == 1'b1) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
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// ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
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// !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage,
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// next different is DS insn, previous different was Jump/Branch
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// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
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//
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always @(posedge clk or posedge rst) begin
|
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if (rst) begin
|
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ex_delayslot_nop <= #1 1'b0;
|
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ex_delayslot_dsi <= #1 1'b0;
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end
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else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
|
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ex_delayslot_nop <= #1 id_void;
|
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ex_delayslot_dsi <= #1 !id_void;
|
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end
|
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else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
|
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ex_delayslot_nop <= #1 1'b0;
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ex_delayslot_dsi <= #1 1'b0;
|
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end
|
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else if (!ex_freeze) begin
|
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ex_delayslot_nop <= #1 id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
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(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
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ex_delayslot_dsi <= #1 !id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
|
(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
|
end
|
|
end
|
|
|
//
|
//
|
// Sign extension of branch offset
|
// Flush pipeline
|
//
|
//
|
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
|
assign if_flushpipe = except_flushpipe | pc_we | extend_flush;
|
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assign id_flushpipe = except_flushpipe | pc_we | extend_flush;
|
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assign ex_flushpipe = except_flushpipe | pc_we | extend_flush;
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assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
|
|
|
|
//
|
|
// EX Sign/Zero extension of immediates
|
|
//
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst)
|
|
ex_simm <= #1 32'h0000_0000;
|
|
else if (!ex_freeze) begin
|
|
ex_simm <= #1 id_simm;
|
|
end
|
|
end
|
|
|
|
//
|
|
// ID Sign/Zero extension of immediate
|
|
//
|
|
always @(id_insn) begin
|
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case (id_insn[31:26]) // synopsys parallel_case
|
|
|
|
// l.addi
|
|
`OR1200_OR32_ADDI:
|
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
|
|
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// l.addic
|
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`OR1200_OR32_ADDIC:
|
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
|
|
|
// l.lxx (load instructions)
|
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`OR1200_OR32_LWZ, `OR1200_OR32_LBZ, `OR1200_OR32_LBS, `OR1200_OR32_LHZ, `OR1200_OR32_LHS:
|
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
|
|
|
// l.muli
|
|
`ifdef OR1200_MULT_IMPLEMENTED
|
|
`OR1200_OR32_MULI:
|
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
|
`endif
|
|
|
|
// l.maci
|
|
`ifdef OR1200_MAC_IMPLEMENTED
|
|
`OR1200_OR32_MACI:
|
|
id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
|
|
`endif
|
|
|
|
// l.mtspr
|
|
`OR1200_OR32_MTSPR:
|
|
id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};
|
|
|
|
// l.sxx (store instructions)
|
|
`OR1200_OR32_SW, `OR1200_OR32_SH, `OR1200_OR32_SB:
|
|
id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
|
|
|
|
// l.xori
|
|
`OR1200_OR32_XORI:
|
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
|
|
|
// l.sfxxi (SFXX with immediate)
|
|
`OR1200_OR32_SFXXI:
|
|
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
|
|
|
|
// Instructions with no or zero extended immediate
|
|
default:
|
|
id_simm = {{16'b0}, id_insn[15:0]};
|
|
|
|
endcase
|
|
end
|
|
|
|
//
|
|
// ID Sign extension of branch offset
|
|
//
|
|
assign id_branch_addrtarget = {{4{id_insn[25]}}, id_insn[25:0]} + id_pc[31:2];
|
|
|
|
//
|
|
// EX Sign extension of branch offset
|
|
//
|
|
|
|
// pipeline ID and EX branch target address
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst)
|
|
ex_branch_addrtarget <= #1 32'h00000000;
|
|
else if (!ex_freeze)
|
|
ex_branch_addrtarget <= #1 id_branch_addrtarget;
|
|
end
|
|
// not pipelined
|
|
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
|
|
|
|
//
|
|
// l.maci in IF stage
|
|
//
|
|
`ifdef OR1200_MAC_IMPLEMENTED
|
|
assign if_maci_op = (if_insn[31:26] == `OR1200_OR32_MACI);
|
|
`else
|
|
assign if_maci_op = 1'b0;
|
|
`endif
|
|
|
//
|
//
|
// l.macrc in ID stage
|
// l.macrc in ID stage
|
//
|
//
|
`ifdef OR1200_MAC_IMPLEMENTED
|
`ifdef OR1200_MAC_IMPLEMENTED
|
| Line 253... |
Line 410... |
`else
|
`else
|
assign id_macrc_op = 1'b0;
|
assign id_macrc_op = 1'b0;
|
`endif
|
`endif
|
|
|
//
|
//
|
|
// l.macrc in EX stage
|
|
//
|
|
`ifdef OR1200_MAC_IMPLEMENTED
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst)
|
|
ex_macrc_op <= #1 1'b0;
|
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
|
ex_macrc_op <= #1 1'b0;
|
|
else if (!ex_freeze)
|
|
ex_macrc_op <= #1 id_macrc_op;
|
|
end
|
|
`else
|
|
assign ex_macrc_op = 1'b0;
|
|
`endif
|
|
|
|
//
|
// cust5_op, cust5_limm (L immediate)
|
// cust5_op, cust5_limm (L immediate)
|
//
|
//
|
assign cust5_op = ex_insn[4:0];
|
assign cust5_op = ex_insn[4:0];
|
assign cust5_limm = ex_insn[10:5];
|
assign cust5_limm = ex_insn[10:5];
|
|
|
//
|
//
|
//
|
//
|
//
|
//
|
assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE);
|
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
|
|
|
//
|
//
|
// Generation of sel_a
|
// Generation of sel_a
|
//
|
//
|
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
|
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
|
| Line 288... |
Line 461... |
sel_b = `OR1200_SEL_WB_FORW;
|
sel_b = `OR1200_SEL_WB_FORW;
|
else
|
else
|
sel_b = `OR1200_SEL_RF;
|
sel_b = `OR1200_SEL_RF;
|
|
|
//
|
//
|
// l.macrc in EX stage
|
|
//
|
|
`ifdef OR1200_MAC_IMPLEMENTED
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst)
|
|
ex_macrc_op <= #1 1'b0;
|
|
else if (!ex_freeze & id_freeze | flushpipe)
|
|
ex_macrc_op <= #1 1'b0;
|
|
else if (!ex_freeze)
|
|
ex_macrc_op <= #1 id_macrc_op;
|
|
end
|
|
`else
|
|
assign ex_macrc_op = 1'b0;
|
|
`endif
|
|
|
|
//
|
|
// Decode of spr_addrimm
|
|
//
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst)
|
|
spr_addrimm <= #1 16'h0000;
|
|
else if (!ex_freeze & id_freeze | flushpipe)
|
|
spr_addrimm <= #1 16'h0000;
|
|
else if (!ex_freeze) begin
|
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
// l.mfspr
|
|
`OR1200_OR32_MFSPR:
|
|
spr_addrimm <= #1 id_insn[15:0];
|
|
// l.mtspr
|
|
default:
|
|
spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
|
|
endcase
|
|
end
|
|
end
|
|
|
|
//
|
|
// Decode of multicycle
|
// Decode of multicycle
|
//
|
//
|
always @(id_insn) begin
|
always @(id_insn) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
`ifdef UNUSED
|
`ifdef UNUSED
|
| Line 361... |
Line 498... |
|
|
// l.sh
|
// l.sh
|
`OR1200_OR32_SH:
|
`OR1200_OR32_SH:
|
multicycle = `OR1200_TWO_CYCLES;
|
multicycle = `OR1200_TWO_CYCLES;
|
`endif
|
`endif
|
|
// l.mfspr
|
|
`OR1200_OR32_MFSPR:
|
|
multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
|
|
|
// ALU instructions except the one with immediate
|
// ALU instructions except the one with immediate
|
`OR1200_OR32_ALU:
|
`OR1200_OR32_ALU:
|
multicycle = id_insn[`OR1200_ALUMCYC_POS];
|
case (id_insn[3:0]) // synopsys parallel_case
|
|
4'h6: multicycle = 2'b11; // l.mul
|
// Single cycle instructions
|
4'h9: multicycle = 2'b10; // l.div
|
default: begin
|
4'hA: multicycle = 2'b10; // l.divu
|
multicycle = `OR1200_ONE_CYCLE;
|
4'hB: multicycle = 2'b11; // l.mulu
|
end
|
default: multicycle = 2'b00;
|
|
|
endcase
|
endcase
|
|
|
end
|
|
|
|
//
|
|
// Decode of imm_signextend
|
|
//
|
|
always @(id_insn) begin
|
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
|
// l.addi
|
|
`OR1200_OR32_ADDI:
|
|
imm_signextend = 1'b1;
|
|
|
|
// l.addic
|
|
`OR1200_OR32_ADDIC:
|
|
imm_signextend = 1'b1;
|
|
|
|
// l.xori
|
|
`OR1200_OR32_XORI:
|
|
imm_signextend = 1'b1;
|
|
|
|
// l.muli
|
|
`ifdef OR1200_MULT_IMPLEMENTED
|
|
`OR1200_OR32_MULI:
|
`OR1200_OR32_MULI:
|
imm_signextend = 1'b1;
|
multicycle = 2'h3;
|
`endif
|
|
|
|
// l.maci
|
|
`ifdef OR1200_MAC_IMPLEMENTED
|
|
`OR1200_OR32_MACI:
|
|
imm_signextend = 1'b1;
|
|
`endif
|
|
|
|
// SFXX insns with immediate
|
|
`OR1200_OR32_SFXXI:
|
|
imm_signextend = 1'b1;
|
|
|
|
// Instructions with no or zero extended immediate
|
// Single cycle instructions
|
default: begin
|
default: begin
|
imm_signextend = 1'b0;
|
multicycle = `OR1200_ONE_CYCLE;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
|
|
|
//
|
|
// LSU addr offset
|
|
//
|
|
always @(lsu_op or ex_insn) begin
|
|
lsu_addrofs[10:0] = ex_insn[10:0];
|
|
case(lsu_op) // synopsys parallel_case
|
|
`OR1200_LSUOP_SW, `OR1200_LSUOP_SH, `OR1200_LSUOP_SB :
|
|
lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};
|
|
default :
|
|
lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};
|
|
endcase
|
|
end
|
end
|
|
|
//
|
//
|
// Register file write address
|
// Register file write address
|
//
|
//
|
| Line 439... |
Line 532... |
if (rst)
|
if (rst)
|
rf_addrw <= #1 5'd0;
|
rf_addrw <= #1 5'd0;
|
else if (!ex_freeze & id_freeze)
|
else if (!ex_freeze & id_freeze)
|
rf_addrw <= #1 5'd00;
|
rf_addrw <= #1 5'd00;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
case (pre_branch_op) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
`OR1200_BRANCHOP_JR, `OR1200_BRANCHOP_BAL:
|
`OR1200_OR32_JAL, `OR1200_OR32_JALR:
|
rf_addrw <= #1 5'd09; // link register r9
|
rf_addrw <= #1 5'd09; // link register r9
|
default:
|
default:
|
rf_addrw <= #1 id_insn[25:21];
|
rf_addrw <= #1 id_insn[25:21];
|
endcase
|
endcase
|
end
|
end
|
| Line 463... |
Line 556... |
// Instruction latch in id_insn
|
// Instruction latch in id_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (flushpipe)
|
else if (id_flushpipe)
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // id_insn[16] must be 1
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> id_insn[16] must be 1
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
id_insn <= #1 if_insn;
|
id_insn <= #1 if_insn;
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: id_insn <= %h", $time, if_insn);
|
$display("%t: id_insn <= %h", $time, if_insn);
|
| Line 481... |
Line 574... |
// Instruction latch in ex_insn
|
// Instruction latch in ex_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // ex_insn[16] must be 1
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> ex_insn[16] must be 1
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_insn <= #1 id_insn;
|
ex_insn <= #1 id_insn;
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: ex_insn <= %h", $time, id_insn);
|
$display("%t: ex_insn <= %h", $time, id_insn);
|
| Line 499... |
Line 592... |
// Instruction latch in wb_insn
|
// Instruction latch in wb_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (flushpipe)
|
// wb_insn should not be changed by exceptions due to correct
|
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // wb_insn[16] must be 1
|
// recording of display_arch_state in the or1200_monitor!
|
|
// wb_insn changed by exception is not used elsewhere!
|
else if (!wb_freeze) begin
|
else if (!wb_freeze) begin
|
wb_insn <= #1 ex_insn;
|
wb_insn <= #1 ex_insn;
|
end
|
end
|
end
|
end
|
|
|
| Line 591... |
Line 685... |
// Decode of except_illegal
|
// Decode of except_illegal
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
except_illegal <= #1 1'b0;
|
except_illegal <= #1 1'b0;
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
except_illegal <= #1 1'b0;
|
except_illegal <= #1 1'b0;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
`OR1200_OR32_J,
|
`OR1200_OR32_J,
|
| Line 631... |
Line 725... |
`OR1200_OR32_MACMSB,
|
`OR1200_OR32_MACMSB,
|
`endif
|
`endif
|
`OR1200_OR32_SW,
|
`OR1200_OR32_SW,
|
`OR1200_OR32_SB,
|
`OR1200_OR32_SB,
|
`OR1200_OR32_SH,
|
`OR1200_OR32_SH,
|
`OR1200_OR32_ALU,
|
|
`OR1200_OR32_SFXX,
|
`OR1200_OR32_SFXX,
|
`ifdef OR1200_OR32_CUST5
|
`ifdef OR1200_OR32_CUST5
|
`OR1200_OR32_CUST5,
|
`OR1200_OR32_CUST5,
|
`endif
|
`endif
|
`OR1200_OR32_NOP:
|
`OR1200_OR32_NOP:
|
except_illegal <= #1 1'b0;
|
except_illegal <= #1 1'b0;
|
|
|
|
`OR1200_OR32_ALU:
|
|
except_illegal <= #1 1'b0
|
|
|
|
`ifdef OR1200_MULT_IMPLEMENTED
|
|
`ifdef OR1200_IMPL_DIV
|
|
`else
|
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
|
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
|
|
`endif
|
|
`else
|
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
|
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
|
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_MUL)
|
|
`endif
|
|
|
|
`ifdef OR1200_IMPL_ADDC
|
|
`else
|
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_ADDC)
|
|
`endif
|
|
|
|
`ifdef OR1200_IMPL_ALU_ROTATE
|
|
`else
|
|
| (({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SHROT) && (id_insn[7:6] == `OR1200_SHROTOP_ROR))
|
|
`endif
|
|
|
|
`ifdef OR1200_IMPL_SUB
|
|
`else
|
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SUB)
|
|
`endif
|
|
;
|
|
|
// Illegal and OR1200 unsupported instructions
|
// Illegal and OR1200 unsupported instructions
|
default:
|
default:
|
except_illegal <= #1 1'b1;
|
except_illegal <= #1 1'b1;
|
|
|
endcase
|
endcase
|
| Line 654... |
Line 778... |
// Decode of alu_op
|
// Decode of alu_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
alu_op <= #1 `OR1200_ALUOP_NOP;
|
alu_op <= #1 `OR1200_ALUOP_NOP;
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
alu_op <= #1 `OR1200_ALUOP_NOP;
|
alu_op <= #1 `OR1200_ALUOP_NOP;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
// l.j
|
|
`OR1200_OR32_J:
|
|
alu_op <= #1 `OR1200_ALUOP_IMM;
|
|
|
|
// j.jal
|
|
`OR1200_OR32_JAL:
|
|
alu_op <= #1 `OR1200_ALUOP_IMM;
|
|
|
|
// l.bnf
|
|
`OR1200_OR32_BNF:
|
|
alu_op <= #1 `OR1200_ALUOP_NOP;
|
|
|
|
// l.bf
|
|
`OR1200_OR32_BF:
|
|
alu_op <= #1 `OR1200_ALUOP_NOP;
|
|
|
|
// l.movhi
|
// l.movhi
|
`OR1200_OR32_MOVHI:
|
`OR1200_OR32_MOVHI:
|
alu_op <= #1 `OR1200_ALUOP_MOVHI;
|
alu_op <= #1 `OR1200_ALUOP_MOVHI;
|
|
|
// l.mfspr
|
|
`OR1200_OR32_MFSPR:
|
|
alu_op <= #1 `OR1200_ALUOP_MFSR;
|
|
|
|
// l.mtspr
|
|
`OR1200_OR32_MTSPR:
|
|
alu_op <= #1 `OR1200_ALUOP_MTSR;
|
|
|
|
// l.addi
|
// l.addi
|
`OR1200_OR32_ADDI:
|
`OR1200_OR32_ADDI:
|
alu_op <= #1 `OR1200_ALUOP_ADD;
|
alu_op <= #1 `OR1200_ALUOP_ADD;
|
|
|
// l.addic
|
// l.addic
|
| Line 746... |
Line 846... |
|
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
|
// Decode of spr_read, spr_write
|
|
//
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst) begin
|
|
spr_read <= #1 1'b0;
|
|
spr_write <= #1 1'b0;
|
|
end
|
|
else if (!ex_freeze & id_freeze | ex_flushpipe) begin
|
|
spr_read <= #1 1'b0;
|
|
spr_write <= #1 1'b0;
|
|
end
|
|
else if (!ex_freeze) begin
|
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
|
// l.mfspr
|
|
`OR1200_OR32_MFSPR: begin
|
|
spr_read <= #1 1'b1;
|
|
spr_write <= #1 1'b0;
|
|
end
|
|
|
|
// l.mtspr
|
|
`OR1200_OR32_MTSPR: begin
|
|
spr_read <= #1 1'b0;
|
|
spr_write <= #1 1'b1;
|
|
end
|
|
|
|
// Default
|
|
default: begin
|
|
spr_read <= #1 1'b0;
|
|
spr_write <= #1 1'b0;
|
|
end
|
|
|
|
endcase
|
|
end
|
|
end
|
|
|
|
//
|
// Decode of mac_op
|
// Decode of mac_op
|
//
|
//
|
`ifdef OR1200_MAC_IMPLEMENTED
|
`ifdef OR1200_MAC_IMPLEMENTED
|
always @(posedge clk or posedge rst) begin
|
always @(id_insn) begin
|
if (rst)
|
|
mac_op <= #1 `OR1200_MACOP_NOP;
|
|
else if (!ex_freeze & id_freeze | flushpipe)
|
|
mac_op <= #1 `OR1200_MACOP_NOP;
|
|
else if (!ex_freeze)
|
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
// l.maci
|
// l.maci
|
`OR1200_OR32_MACI:
|
`OR1200_OR32_MACI:
|
mac_op <= #1 `OR1200_MACOP_MAC;
|
id_mac_op <= #1 `OR1200_MACOP_MAC;
|
|
|
// l.nop
|
// l.mac, l.msb
|
`OR1200_OR32_MACMSB:
|
`OR1200_OR32_MACMSB:
|
mac_op <= #1 id_insn[1:0];
|
id_mac_op <= #1 id_insn[2:0];
|
|
|
// Illegal and OR1200 unsupported instructions
|
// Illegal and OR1200 unsupported instructions
|
default: begin
|
default:
|
mac_op <= #1 `OR1200_MACOP_NOP;
|
id_mac_op <= #1 `OR1200_MACOP_NOP;
|
end
|
|
|
|
endcase
|
endcase
|
else
|
|
mac_op <= #1 `OR1200_MACOP_NOP;
|
|
end
|
end
|
|
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst)
|
|
ex_mac_op <= #1 `OR1200_MACOP_NOP;
|
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
|
ex_mac_op <= #1 `OR1200_MACOP_NOP;
|
|
else if (!ex_freeze)
|
|
ex_mac_op <= #1 id_mac_op;
|
|
end
|
|
|
|
assign mac_op = abort_mvspr ? `OR1200_MACOP_NOP : ex_mac_op;
|
`else
|
`else
|
|
assign id_mac_op = `OR1200_MACOP_NOP;
|
assign mac_op = `OR1200_MACOP_NOP;
|
assign mac_op = `OR1200_MACOP_NOP;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Decode of shrot_op
|
// Decode of shrot_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
shrot_op <= #1 `OR1200_SHROTOP_NOP;
|
shrot_op <= #1 `OR1200_SHROTOP_NOP;
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
shrot_op <= #1 `OR1200_SHROTOP_NOP;
|
shrot_op <= #1 `OR1200_SHROTOP_NOP;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
shrot_op <= #1 id_insn[`OR1200_SHROTOP_POS];
|
shrot_op <= #1 id_insn[`OR1200_SHROTOP_POS];
|
end
|
end
|
end
|
end
|
| Line 797... |
Line 938... |
// Decode of rfwb_op
|
// Decode of rfwb_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
|
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
|
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
// j.jal
|
// j.jal
|
| Line 879... |
Line 1020... |
`OR1200_OR32_CUST5:
|
`OR1200_OR32_CUST5:
|
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
|
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
|
`endif
|
`endif
|
|
|
// Instructions w/o register-file write-back
|
// Instructions w/o register-file write-back
|
default: begin
|
default:
|
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
|
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
|
end
|
|
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Decode of pre_branch_op
|
// Decode of id_branch_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
id_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
else if (flushpipe)
|
else if (id_flushpipe)
|
pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
id_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
case (if_insn[31:26]) // synopsys parallel_case
|
case (if_insn[31:26]) // synopsys parallel_case
|
|
|
// l.j
|
// l.j
|
`OR1200_OR32_J:
|
`OR1200_OR32_J:
|
pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
|
id_branch_op <= #1 `OR1200_BRANCHOP_J;
|
|
|
// j.jal
|
// j.jal
|
`OR1200_OR32_JAL:
|
`OR1200_OR32_JAL:
|
pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
|
id_branch_op <= #1 `OR1200_BRANCHOP_J;
|
|
|
// j.jalr
|
// j.jalr
|
`OR1200_OR32_JALR:
|
`OR1200_OR32_JALR:
|
pre_branch_op <= #1 `OR1200_BRANCHOP_JR;
|
id_branch_op <= #1 `OR1200_BRANCHOP_JR;
|
|
|
// l.jr
|
// l.jr
|
`OR1200_OR32_JR:
|
`OR1200_OR32_JR:
|
pre_branch_op <= #1 `OR1200_BRANCHOP_JR;
|
id_branch_op <= #1 `OR1200_BRANCHOP_JR;
|
|
|
// l.bnf
|
// l.bnf
|
`OR1200_OR32_BNF:
|
`OR1200_OR32_BNF:
|
pre_branch_op <= #1 `OR1200_BRANCHOP_BNF;
|
id_branch_op <= #1 `OR1200_BRANCHOP_BNF;
|
|
|
// l.bf
|
// l.bf
|
`OR1200_OR32_BF:
|
`OR1200_OR32_BF:
|
pre_branch_op <= #1 `OR1200_BRANCHOP_BF;
|
id_branch_op <= #1 `OR1200_BRANCHOP_BF;
|
|
|
// l.rfe
|
// l.rfe
|
`OR1200_OR32_RFE:
|
`OR1200_OR32_RFE:
|
pre_branch_op <= #1 `OR1200_BRANCHOP_RFE;
|
id_branch_op <= #1 `OR1200_BRANCHOP_RFE;
|
|
|
// Non branch instructions
|
// Non branch instructions
|
default: begin
|
default:
|
pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
id_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
end
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Generation of branch_op
|
// Generation of ex_branch_op
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
ex_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
ex_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
branch_op <= #1 pre_branch_op;
|
ex_branch_op <= #1 id_branch_op;
|
|
|
//
|
//
|
// Decode of lsu_op
|
// Decode of id_lsu_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(id_insn) begin
|
if (rst)
|
|
lsu_op <= #1 `OR1200_LSUOP_NOP;
|
|
else if (!ex_freeze & id_freeze | flushpipe)
|
|
lsu_op <= #1 `OR1200_LSUOP_NOP;
|
|
else if (!ex_freeze) begin
|
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
// l.lwz
|
// l.lwz
|
`OR1200_OR32_LWZ:
|
`OR1200_OR32_LWZ:
|
lsu_op <= #1 `OR1200_LSUOP_LWZ;
|
id_lsu_op <= #1 `OR1200_LSUOP_LWZ;
|
|
|
// l.lbz
|
// l.lbz
|
`OR1200_OR32_LBZ:
|
`OR1200_OR32_LBZ:
|
lsu_op <= #1 `OR1200_LSUOP_LBZ;
|
id_lsu_op <= #1 `OR1200_LSUOP_LBZ;
|
|
|
// l.lbs
|
// l.lbs
|
`OR1200_OR32_LBS:
|
`OR1200_OR32_LBS:
|
lsu_op <= #1 `OR1200_LSUOP_LBS;
|
id_lsu_op <= #1 `OR1200_LSUOP_LBS;
|
|
|
// l.lhz
|
// l.lhz
|
`OR1200_OR32_LHZ:
|
`OR1200_OR32_LHZ:
|
lsu_op <= #1 `OR1200_LSUOP_LHZ;
|
id_lsu_op <= #1 `OR1200_LSUOP_LHZ;
|
|
|
// l.lhs
|
// l.lhs
|
`OR1200_OR32_LHS:
|
`OR1200_OR32_LHS:
|
lsu_op <= #1 `OR1200_LSUOP_LHS;
|
id_lsu_op <= #1 `OR1200_LSUOP_LHS;
|
|
|
// l.sw
|
// l.sw
|
`OR1200_OR32_SW:
|
`OR1200_OR32_SW:
|
lsu_op <= #1 `OR1200_LSUOP_SW;
|
id_lsu_op <= #1 `OR1200_LSUOP_SW;
|
|
|
// l.sb
|
// l.sb
|
`OR1200_OR32_SB:
|
`OR1200_OR32_SB:
|
lsu_op <= #1 `OR1200_LSUOP_SB;
|
id_lsu_op <= #1 `OR1200_LSUOP_SB;
|
|
|
// l.sh
|
// l.sh
|
`OR1200_OR32_SH:
|
`OR1200_OR32_SH:
|
lsu_op <= #1 `OR1200_LSUOP_SH;
|
id_lsu_op <= #1 `OR1200_LSUOP_SH;
|
|
|
// Non load/store instructions
|
// Non load/store instructions
|
default: begin
|
default:
|
lsu_op <= #1 `OR1200_LSUOP_NOP;
|
id_lsu_op <= #1 `OR1200_LSUOP_NOP;
|
end
|
|
endcase
|
endcase
|
end
|
end
|
end
|
|
|
|
//
|
//
|
// Decode of comp_op
|
// Decode of comp_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
comp_op <= #1 4'd0;
|
comp_op <= #1 4'd0;
|
end else if (!ex_freeze & id_freeze | flushpipe)
|
end else if (!ex_freeze & id_freeze | ex_flushpipe)
|
comp_op <= #1 4'd0;
|
comp_op <= #1 4'd0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
comp_op <= #1 id_insn[24:21];
|
comp_op <= #1 id_insn[24:21];
|
end
|
end
|
|
|
| Line 1014... |
Line 1149... |
// Decode of l.sys
|
// Decode of l.sys
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
sig_syscall <= #1 1'b0;
|
sig_syscall <= #1 1'b0;
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
sig_syscall <= #1 1'b0;
|
sig_syscall <= #1 1'b0;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
|
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
|
| Line 1033... |
Line 1168... |
// Decode of l.trap
|
// Decode of l.trap
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
sig_trap <= #1 1'b0;
|
sig_trap <= #1 1'b0;
|
else if (!ex_freeze & id_freeze | flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
sig_trap <= #1 1'b0;
|
sig_trap <= #1 1'b0;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
|
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
|
