| Line 77... |
Line 77... |
// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
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input ex_freeze /* verilator public */;
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input wb_freeze;
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input wb_freeze /* verilator public */;
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output if_flushpipe;
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output if_flushpipe;
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output id_flushpipe;
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output id_flushpipe;
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output ex_flushpipe;
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output ex_flushpipe;
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output wb_flushpipe;
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output wb_flushpipe;
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input extend_flush;
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input extend_flush;
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input except_flushpipe;
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input except_flushpipe;
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input abort_mvspr ;
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input abort_mvspr ;
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input [31:0] if_insn;
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input [31:0] if_insn;
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output [31:0] id_insn;
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output [31:0] id_insn;
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output [31:0] ex_insn;
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output [31:0] ex_insn /* verilator public */;
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output [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
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output [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
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output [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
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output [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
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input ex_branch_taken;
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input ex_branch_taken;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
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| Line 153... |
Line 153... |
`else
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`else
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire ex_macrc_op;
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wire ex_macrc_op;
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`endif
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`endif
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reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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reg [31:0] id_insn;
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reg [31:0] id_insn /* verilator public */;
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reg [31:0] ex_insn;
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reg [31:0] ex_insn /* verilator public */;
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reg [31:0] wb_insn;
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reg [31:0] wb_insn /* verilator public */;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
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reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
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reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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reg [`OR1200_SEL_WIDTH-1:0] sel_a;
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reg [`OR1200_SEL_WIDTH-1:0] sel_a;
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reg [`OR1200_SEL_WIDTH-1:0] sel_b;
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reg [`OR1200_SEL_WIDTH-1:0] sel_b;
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| Line 371... |
Line 371... |
//
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//
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//
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//
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//
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//
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assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
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assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
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`ifdef verilator
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// Function to access wb_insn (for Verilator). Have to hide this from
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// simulator, since functions with no inputs are not allowed in IEEE
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// 1364-2001.
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function [31:0] get_wb_insn;
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// verilator public
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get_wb_insn = wb_insn;
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endfunction // get_wb_insn
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// Function to access id_insn (for Verilator). Have to hide this from
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// simulator, since functions with no inputs are not allowed in IEEE
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// 1364-2001.
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function [31:0] get_id_insn;
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// verilator public
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get_id_insn = id_insn;
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endfunction // get_id_insn
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|
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// Function to access ex_insn (for Verilator). Have to hide this from
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// simulator, since functions with no inputs are not allowed in IEEE
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// 1364-2001.
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function [31:0] get_ex_insn;
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// verilator public
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get_ex_insn = ex_insn;
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endfunction // get_ex_insn
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`endif
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//
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//
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// Generation of sel_a
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// Generation of sel_a
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//
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//
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always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
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always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
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if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
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if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
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| Line 859... |
Line 888... |
always @(id_insn) begin
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always @(id_insn) begin
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case (id_insn[31:26]) // synopsys parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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// l.maci
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// l.maci
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`OR1200_OR32_MACI:
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`OR1200_OR32_MACI:
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id_mac_op <= `OR1200_MACOP_MAC;
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id_mac_op = `OR1200_MACOP_MAC;
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|
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// l.mac, l.msb
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// l.mac, l.msb
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`OR1200_OR32_MACMSB:
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`OR1200_OR32_MACMSB:
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id_mac_op <= id_insn[2:0];
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id_mac_op = id_insn[2:0];
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|
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// Illegal and OR1200 unsupported instructions
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// Illegal and OR1200 unsupported instructions
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default:
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default:
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id_mac_op <= `OR1200_MACOP_NOP;
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id_mac_op = `OR1200_MACOP_NOP;
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|
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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| Line 1066... |
Line 1095... |
always @(id_insn) begin
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always @(id_insn) begin
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case (id_insn[31:26]) // synopsys parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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|
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// l.lwz
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// l.lwz
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`OR1200_OR32_LWZ:
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`OR1200_OR32_LWZ:
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id_lsu_op <= `OR1200_LSUOP_LWZ;
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id_lsu_op = `OR1200_LSUOP_LWZ;
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|
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// l.lbz
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// l.lbz
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`OR1200_OR32_LBZ:
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`OR1200_OR32_LBZ:
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id_lsu_op <= `OR1200_LSUOP_LBZ;
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id_lsu_op = `OR1200_LSUOP_LBZ;
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// l.lbs
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// l.lbs
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`OR1200_OR32_LBS:
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`OR1200_OR32_LBS:
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id_lsu_op <= `OR1200_LSUOP_LBS;
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id_lsu_op = `OR1200_LSUOP_LBS;
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// l.lhz
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// l.lhz
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`OR1200_OR32_LHZ:
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`OR1200_OR32_LHZ:
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id_lsu_op <= `OR1200_LSUOP_LHZ;
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id_lsu_op = `OR1200_LSUOP_LHZ;
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|
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// l.lhs
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// l.lhs
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`OR1200_OR32_LHS:
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`OR1200_OR32_LHS:
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id_lsu_op <= `OR1200_LSUOP_LHS;
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id_lsu_op = `OR1200_LSUOP_LHS;
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// l.sw
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// l.sw
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`OR1200_OR32_SW:
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`OR1200_OR32_SW:
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id_lsu_op <= `OR1200_LSUOP_SW;
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id_lsu_op = `OR1200_LSUOP_SW;
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|
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// l.sb
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// l.sb
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`OR1200_OR32_SB:
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`OR1200_OR32_SB:
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id_lsu_op <= `OR1200_LSUOP_SB;
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id_lsu_op = `OR1200_LSUOP_SB;
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|
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// l.sh
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// l.sh
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`OR1200_OR32_SH:
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`OR1200_OR32_SH:
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id_lsu_op <= `OR1200_LSUOP_SH;
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id_lsu_op = `OR1200_LSUOP_SH;
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// Non load/store instructions
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// Non load/store instructions
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default:
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default:
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id_lsu_op <= `OR1200_LSUOP_NOP;
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id_lsu_op = `OR1200_LSUOP_NOP;
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endcase
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endcase
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end
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end
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//
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//
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