| Line 214... |
Line 214... |
// ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
|
// ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
|
// !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage,
|
// !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage,
|
// next different is DS insn, previous different was Jump/Branch
|
// next different is DS insn, previous different was Jump/Branch
|
// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
|
// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
ex_delayslot_nop <= 1'b0;
|
ex_delayslot_nop <= 1'b0;
|
ex_delayslot_dsi <= 1'b0;
|
ex_delayslot_dsi <= 1'b0;
|
end
|
end
|
else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
|
else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
|
ex_delayslot_nop <= id_void;
|
ex_delayslot_nop <= id_void;
|
| Line 246... |
Line 246... |
assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
|
assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
|
|
|
//
|
//
|
// EX Sign/Zero extension of immediates
|
// EX Sign/Zero extension of immediates
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
ex_simm <= 32'h0000_0000;
|
ex_simm <= 32'h0000_0000;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_simm <= id_simm;
|
ex_simm <= id_simm;
|
end
|
end
|
end
|
end
|
| Line 317... |
Line 317... |
//
|
//
|
// EX Sign extension of branch offset
|
// EX Sign extension of branch offset
|
//
|
//
|
|
|
// pipeline ID and EX branch target address
|
// pipeline ID and EX branch target address
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
ex_branch_addrtarget <= 32'h00000000;
|
ex_branch_addrtarget <= 32'h00000000;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_branch_addrtarget <= id_branch_addrtarget;
|
ex_branch_addrtarget <= id_branch_addrtarget;
|
end
|
end
|
// not pipelined
|
// not pipelined
|
| Line 348... |
Line 348... |
|
|
//
|
//
|
// l.macrc in EX stage
|
// l.macrc in EX stage
|
//
|
//
|
`ifdef OR1200_MAC_IMPLEMENTED
|
`ifdef OR1200_MAC_IMPLEMENTED
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
ex_macrc_op <= 1'b0;
|
ex_macrc_op <= 1'b0;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
ex_macrc_op <= 1'b0;
|
ex_macrc_op <= 1'b0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_macrc_op <= id_macrc_op;
|
ex_macrc_op <= id_macrc_op;
|
| Line 514... |
Line 514... |
|
|
|
|
//
|
//
|
// Register file write address
|
// Register file write address
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
rf_addrw <= 5'd0;
|
rf_addrw <= 5'd0;
|
else if (!ex_freeze & id_freeze)
|
else if (!ex_freeze & id_freeze)
|
rf_addrw <= 5'd00;
|
rf_addrw <= 5'd00;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
| Line 531... |
Line 531... |
end
|
end
|
|
|
//
|
//
|
// rf_addrw in wb stage (used in forwarding logic)
|
// rf_addrw in wb stage (used in forwarding logic)
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
wb_rfaddrw <= 5'd0;
|
wb_rfaddrw <= 5'd0;
|
else if (!wb_freeze)
|
else if (!wb_freeze)
|
wb_rfaddrw <= rf_addrw;
|
wb_rfaddrw <= rf_addrw;
|
end
|
end
|
|
|
//
|
//
|
// Instruction latch in id_insn
|
// Instruction latch in id_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
|
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (id_flushpipe)
|
else if (id_flushpipe)
|
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> id_insn[16] must be 1
|
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> id_insn[16] must be 1
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
id_insn <= if_insn;
|
id_insn <= if_insn;
|
| Line 559... |
Line 559... |
end
|
end
|
|
|
//
|
//
|
// Instruction latch in ex_insn
|
// Instruction latch in ex_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
|
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> ex_insn[16] must be 1
|
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> ex_insn[16] must be 1
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_insn <= id_insn;
|
ex_insn <= id_insn;
|
| Line 577... |
Line 577... |
end
|
end
|
|
|
//
|
//
|
// Instruction latch in wb_insn
|
// Instruction latch in wb_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
wb_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
|
wb_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
|
// wb_insn should not be changed by exceptions due to correct
|
// wb_insn should not be changed by exceptions due to correct
|
// recording of display_arch_state in the or1200_monitor!
|
// recording of display_arch_state in the or1200_monitor!
|
// wb_insn changed by exception is not used elsewhere!
|
// wb_insn changed by exception is not used elsewhere!
|
else if (!wb_freeze) begin
|
else if (!wb_freeze) begin
|
| Line 591... |
Line 591... |
end
|
end
|
|
|
//
|
//
|
// Decode of sel_imm
|
// Decode of sel_imm
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
sel_imm <= 1'b0;
|
sel_imm <= 1'b0;
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
case (if_insn[31:26]) // synopsys parallel_case
|
case (if_insn[31:26]) // synopsys parallel_case
|
|
|
// j.jalr
|
// j.jalr
|
| Line 674... |
Line 674... |
end
|
end
|
|
|
//
|
//
|
// Decode of except_illegal
|
// Decode of except_illegal
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
except_illegal <= 1'b0;
|
except_illegal <= 1'b0;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
except_illegal <= 1'b0;
|
except_illegal <= 1'b0;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
| Line 772... |
Line 772... |
end
|
end
|
|
|
//
|
//
|
// Decode of alu_op
|
// Decode of alu_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
alu_op <= `OR1200_ALUOP_NOP;
|
alu_op <= `OR1200_ALUOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
alu_op <= `OR1200_ALUOP_NOP;
|
alu_op <= `OR1200_ALUOP_NOP;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
| Line 845... |
Line 845... |
end
|
end
|
|
|
//
|
//
|
// Decode of spr_read, spr_write
|
// Decode of spr_read, spr_write
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
spr_read <= 1'b0;
|
spr_read <= 1'b0;
|
spr_write <= 1'b0;
|
spr_write <= 1'b0;
|
end
|
end
|
else if (!ex_freeze & id_freeze | ex_flushpipe) begin
|
else if (!ex_freeze & id_freeze | ex_flushpipe) begin
|
spr_read <= 1'b0;
|
spr_read <= 1'b0;
|
| Line 901... |
Line 901... |
id_mac_op = `OR1200_MACOP_NOP;
|
id_mac_op = `OR1200_MACOP_NOP;
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
ex_mac_op <= `OR1200_MACOP_NOP;
|
ex_mac_op <= `OR1200_MACOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
ex_mac_op <= `OR1200_MACOP_NOP;
|
ex_mac_op <= `OR1200_MACOP_NOP;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_mac_op <= id_mac_op;
|
ex_mac_op <= id_mac_op;
|
| Line 919... |
Line 919... |
`endif
|
`endif
|
|
|
//
|
//
|
// Decode of shrot_op
|
// Decode of shrot_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
shrot_op <= `OR1200_SHROTOP_NOP;
|
shrot_op <= `OR1200_SHROTOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
shrot_op <= `OR1200_SHROTOP_NOP;
|
shrot_op <= `OR1200_SHROTOP_NOP;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
shrot_op <= id_insn[`OR1200_SHROTOP_POS];
|
shrot_op <= id_insn[`OR1200_SHROTOP_POS];
|
| Line 932... |
Line 932... |
end
|
end
|
|
|
//
|
//
|
// Decode of rfwb_op
|
// Decode of rfwb_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
rfwb_op <= `OR1200_RFWBOP_NOP;
|
rfwb_op <= `OR1200_RFWBOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
rfwb_op <= `OR1200_RFWBOP_NOP;
|
rfwb_op <= `OR1200_RFWBOP_NOP;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
| Line 1032... |
Line 1032... |
end
|
end
|
|
|
//
|
//
|
// Decode of id_branch_op
|
// Decode of id_branch_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
id_branch_op <= `OR1200_BRANCHOP_NOP;
|
id_branch_op <= `OR1200_BRANCHOP_NOP;
|
else if (id_flushpipe)
|
else if (id_flushpipe)
|
id_branch_op <= `OR1200_BRANCHOP_NOP;
|
id_branch_op <= `OR1200_BRANCHOP_NOP;
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
case (if_insn[31:26]) // synopsys parallel_case
|
case (if_insn[31:26]) // synopsys parallel_case
|
| Line 1079... |
Line 1079... |
end
|
end
|
|
|
//
|
//
|
// Generation of ex_branch_op
|
// Generation of ex_branch_op
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
ex_branch_op <= `OR1200_BRANCHOP_NOP;
|
ex_branch_op <= `OR1200_BRANCHOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
ex_branch_op <= `OR1200_BRANCHOP_NOP;
|
ex_branch_op <= `OR1200_BRANCHOP_NOP;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_branch_op <= id_branch_op;
|
ex_branch_op <= id_branch_op;
|
| Line 1135... |
Line 1135... |
end
|
end
|
|
|
//
|
//
|
// Decode of comp_op
|
// Decode of comp_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
comp_op <= 4'd0;
|
comp_op <= 4'd0;
|
end else if (!ex_freeze & id_freeze | ex_flushpipe)
|
end else if (!ex_freeze & id_freeze | ex_flushpipe)
|
comp_op <= 4'd0;
|
comp_op <= 4'd0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
comp_op <= id_insn[24:21];
|
comp_op <= id_insn[24:21];
|
| Line 1158... |
Line 1158... |
|
|
|
|
//
|
//
|
// Decode of l.sys
|
// Decode of l.sys
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
sig_syscall <= 1'b0;
|
sig_syscall <= 1'b0;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
sig_syscall <= 1'b0;
|
sig_syscall <= 1'b0;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
| Line 1177... |
Line 1177... |
end
|
end
|
|
|
//
|
//
|
// Decode of l.trap
|
// Decode of l.trap
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
sig_trap <= 1'b0;
|
sig_trap <= 1'b0;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
sig_trap <= 1'b0;
|
sig_trap <= 1'b0;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
| Line 1197... |
Line 1197... |
end
|
end
|
|
|
// Decode destination register address for data cache to check if store ops
|
// Decode destination register address for data cache to check if store ops
|
// are being done from the stack register (r1) or frame pointer register (r2)
|
// are being done from the stack register (r1) or frame pointer register (r2)
|
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
|
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst)
|
if (rst == `OR1200_RST_VALUE)
|
dc_no_writethrough <= 0;
|
dc_no_writethrough <= 0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
dc_no_writethrough <= (id_insn[20:16] == 5'd1) | (id_insn[20:16] == 5'd2);
|
dc_no_writethrough <= (id_insn[20:16] == 5'd1) | (id_insn[20:16] == 5'd2);
|
end
|
end
|
`else
|
`else
|
