| Line 319... |
Line 319... |
//
|
//
|
|
|
// pipeline ID and EX branch target address
|
// pipeline ID and EX branch target address
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
ex_branch_addrtarget <= 32'h00000000;
|
ex_branch_addrtarget <= 0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_branch_addrtarget <= id_branch_addrtarget;
|
ex_branch_addrtarget <= id_branch_addrtarget;
|
end
|
end
|
// not pipelined
|
// not pipelined
|
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
|
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
|
| Line 469... |
Line 469... |
multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
|
multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
|
|
|
// ALU instructions except the one with immediate
|
// ALU instructions except the one with immediate
|
`OR1200_OR32_ALU:
|
`OR1200_OR32_ALU:
|
case (id_insn[3:0]) // synopsys parallel_case
|
case (id_insn[3:0]) // synopsys parallel_case
|
4'h6: multicycle = 2'b11; // l.mul
|
4'h6: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mul
|
4'h9: multicycle = 2'b10; // l.div
|
4'h9: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.div
|
4'hA: multicycle = 2'b10; // l.divu
|
4'hA: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.divu
|
4'hB: multicycle = 2'b11; // l.mulu
|
4'hB: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mulu
|
default: multicycle = 2'b00;
|
default: multicycle = `OR1200_MULTICYCLE_WIDTH'd0;
|
endcase
|
endcase
|
|
|
`OR1200_OR32_MULI:
|
`OR1200_OR32_MULI:
|
multicycle = 2'h3;
|
multicycle = `OR1200_MULTICYCLE_WIDTH'd3;
|
|
|
// Single cycle instructions
|
// Single cycle instructions
|
default: begin
|
default: begin
|
multicycle = `OR1200_ONE_CYCLE;
|
multicycle = `OR1200_ONE_CYCLE;
|
end
|
end
|
| Line 735... |
Line 734... |
except_illegal <= 1'b0
|
except_illegal <= 1'b0
|
|
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_DIV_IMPLEMENTED
|
`ifdef OR1200_DIV_IMPLEMENTED
|
`else
|
`else
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
|
| (id_insn[3:0] == `OR1200_ALUOP_DIV)
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
|
| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
|
`endif
|
`endif
|
`else
|
`else
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
|
| (id_insn[3:0] == `OR1200_ALUOP_DIV)
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
|
| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_MUL)
|
| (id_insn[3:0] == `OR1200_ALUOP_MUL)
|
`endif
|
`endif
|
|
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
`else
|
`else
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_ADDC)
|
| (id_insn[3:0] == `OR1200_ALUOP_ADDC)
|
`endif
|
`endif
|
|
|
`ifdef OR1200_IMPL_ALU_ROTATE
|
`ifdef OR1200_IMPL_ALU_ROTATE
|
`else
|
`else
|
| (({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SHROT) && (id_insn[7:6] == `OR1200_SHROTOP_ROR))
|
| ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
|
|
(id_insn[7:6] == `OR1200_SHROTOP_ROR))
|
`endif
|
`endif
|
|
|
`ifdef OR1200_IMPL_SUB
|
`ifdef OR1200_IMPL_SUB
|
`else
|
`else
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SUB)
|
| (id_insn[3:0] == `OR1200_ALUOP_SUB)
|
`endif
|
`endif
|
;
|
;
|
|
|
// Illegal and OR1200 unsupported instructions
|
// Illegal and OR1200 unsupported instructions
|
default:
|
default:
|
except_illegal <= 1'b1;
|
except_illegal <= 1'b1;
|
|
|
endcase
|
endcase
|
|
end // if (!ex_freeze)
|
end
|
|
end
|
end
|
|
|
|
|
//
|
//
|
// Decode of alu_op
|
// Decode of alu_op
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
