Line 60... |
Line 60... |
// Internal i/f
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// Internal i/f
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except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
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except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
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wb_flushpipe,
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wb_flushpipe,
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id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
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id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
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id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
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id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
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rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op,
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rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, alu_op2, mac_op, shrot_op,
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rf_addrw, rfwb_op, fpu_op,
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comp_op, rf_addrw, rfwb_op, fpu_op,
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wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
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wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
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sel_b, id_lsu_op,
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sel_b, id_lsu_op,
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cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
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cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
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multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
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multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
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force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
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force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
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Line 98... |
Line 98... |
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
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output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
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output rf_rda;
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output rf_rda;
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output rf_rdb;
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output rf_rdb;
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output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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output [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
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output [`OR1200_MACOP_WIDTH-1:0] mac_op;
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output [`OR1200_MACOP_WIDTH-1:0] mac_op;
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output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
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output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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output [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
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output [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
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input pc_we;
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input pc_we;
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Line 142... |
Line 143... |
// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
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reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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reg [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
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wire if_maci_op;
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wire if_maci_op;
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`ifdef OR1200_MAC_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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reg [`OR1200_MACOP_WIDTH-1:0] ex_mac_op;
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reg [`OR1200_MACOP_WIDTH-1:0] ex_mac_op;
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reg [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
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reg [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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Line 748... |
Line 750... |
`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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`else
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`else
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| (id_insn[3:0] == `OR1200_ALUOP_ADDC)
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| (id_insn[3:0] == `OR1200_ALUOP_ADDC)
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`endif
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`endif
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|
|
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`ifdef OR1200_IMPL_ALU_FFL1
|
|
`else
|
|
| (id_insn[3:0] == `OR1200_ALUOP_FFL1)
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|
`endif
|
|
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`ifdef OR1200_IMPL_ALU_ROTATE
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`ifdef OR1200_IMPL_ALU_ROTATE
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`else
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`else
|
| ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
|
| ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
|
(id_insn[7:6] == `OR1200_SHROTOP_ROR))
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(id_insn[7:6] == `OR1200_SHROTOP_ROR))
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`endif
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`endif
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Line 842... |
Line 849... |
endcase
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endcase
|
|
|
end
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end
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end
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end
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|
|
|
|
|
//
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|
// Decode of alu_op2 (field of bits 9:8)
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|
//
|
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
|
if (rst == `OR1200_RST_VALUE)
|
|
alu_op2 <= 0;
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|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
|
alu_op2 <= 0;
|
|
else if (!ex_freeze) begin
|
|
alu_op2 <= id_insn[`OR1200_ALUOP2_POS];
|
|
end
|
|
end
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|
|
|
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//
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//
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// Decode of spr_read, spr_write
|
// Decode of spr_read, spr_write
|
//
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//
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
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if (rst == `OR1200_RST_VALUE) begin
|