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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Diff between revs 640 and 644

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Rev 640 Rev 644
Line 436... Line 436...
//
//
// Decode of multicycle
// Decode of multicycle
//
//
always @(id_insn) begin
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys parallel_case
  case (id_insn[31:26])         // synopsys parallel_case
 
    // l.rfe
 
    `OR1200_OR32_RFE,
    // l.mfspr
    // l.mfspr
    `OR1200_OR32_MFSPR:
    `OR1200_OR32_MFSPR:
      multicycle = `OR1200_TWO_CYCLES;  // to read from ITLB/DTLB (sync RAMs)
      multicycle = `OR1200_TWO_CYCLES;  // to read from ITLB/DTLB (sync RAMs)
    // Single cycle instructions
    // Single cycle instructions
    default: begin
    default: begin

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