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//
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//
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// Decode of multicycle
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// Decode of multicycle
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//
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//
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always @(id_insn) begin
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always @(id_insn) begin
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case (id_insn[31:26]) // synopsys parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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// l.rfe
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`OR1200_OR32_RFE,
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// l.mfspr
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// l.mfspr
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`OR1200_OR32_MFSPR:
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`OR1200_OR32_MFSPR:
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multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
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multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
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// Single cycle instructions
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// Single cycle instructions
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default: begin
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default: begin
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