| Line 67... |
Line 67... |
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
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wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
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sel_b, id_lsu_op,
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sel_b, id_lsu_op,
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cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
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cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
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multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
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multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
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force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
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force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
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ex_spr_write,
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ex_spr_write, du_flush_pipe,
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id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal, dc_no_writethrough
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id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal, dc_no_writethrough
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);
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);
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|
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//
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//
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// I/O
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// I/O
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| Line 134... |
Line 134... |
output id_macrc_op;
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output id_macrc_op;
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output ex_macrc_op;
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output ex_macrc_op;
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output rfe;
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output rfe;
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output except_illegal;
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output except_illegal;
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output dc_no_writethrough;
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output dc_no_writethrough;
|
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input du_flush_pipe;
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|
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
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reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
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| Line 242... |
Line 242... |
end
|
end
|
|
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//
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//
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// Flush pipeline
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// Flush pipeline
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//
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//
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assign if_flushpipe = except_flushpipe | pc_we | extend_flush;
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assign if_flushpipe = except_flushpipe | pc_we | extend_flush | du_flush_pipe;
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assign id_flushpipe = except_flushpipe | pc_we | extend_flush;
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assign id_flushpipe = except_flushpipe | pc_we | extend_flush | du_flush_pipe;
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assign ex_flushpipe = except_flushpipe | pc_we | extend_flush;
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assign ex_flushpipe = except_flushpipe | pc_we | extend_flush | du_flush_pipe;
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assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
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assign wb_flushpipe = except_flushpipe | pc_we | extend_flush | du_flush_pipe;
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|
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//
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//
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// EX Sign/Zero extension of immediates
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// EX Sign/Zero extension of immediates
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
