| Line 65... |
Line 65... |
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op,
|
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op,
|
rf_addrw, rfwb_op, fpu_op,
|
rf_addrw, rfwb_op, fpu_op,
|
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
|
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
|
sel_b, id_lsu_op,
|
sel_b, id_lsu_op,
|
cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
|
cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
|
multicycle, wbforw_valid, sig_syscall, sig_trap,
|
multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
|
force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
|
force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
|
ex_spr_write,
|
ex_spr_write,
|
id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal
|
id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal, dc_no_writethrough
|
);
|
);
|
|
|
//
|
//
|
// I/O
|
// I/O
|
//
|
//
|
| Line 111... |
Line 111... |
output [`OR1200_SEL_WIDTH-1:0] sel_a;
|
output [`OR1200_SEL_WIDTH-1:0] sel_a;
|
output [`OR1200_SEL_WIDTH-1:0] sel_b;
|
output [`OR1200_SEL_WIDTH-1:0] sel_b;
|
output [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
|
output [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
|
output [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
output [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
|
output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
|
|
output [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
|
output [4:0] cust5_op;
|
output [4:0] cust5_op;
|
output [5:0] cust5_limm;
|
output [5:0] cust5_limm;
|
input [31:0] id_pc;
|
input [31:0] id_pc;
|
input [31:0] ex_pc;
|
input [31:0] ex_pc;
|
output [31:0] id_simm;
|
output [31:0] id_simm;
|
| Line 132... |
Line 133... |
output [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
|
output [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
|
output id_macrc_op;
|
output id_macrc_op;
|
output ex_macrc_op;
|
output ex_macrc_op;
|
output rfe;
|
output rfe;
|
output except_illegal;
|
output except_illegal;
|
|
output dc_no_writethrough;
|
|
|
|
|
//
|
//
|
// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
|
reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
|
| Line 162... |
Line 165... |
reg [`OR1200_SEL_WIDTH-1:0] sel_b;
|
reg [`OR1200_SEL_WIDTH-1:0] sel_b;
|
reg sel_imm;
|
reg sel_imm;
|
reg [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
|
reg [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
|
reg [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
reg [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
|
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
|
|
reg [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
|
reg [31:0] id_simm;
|
reg [31:0] id_simm;
|
reg [31:0] ex_simm;
|
reg [31:0] ex_simm;
|
reg sig_syscall;
|
reg sig_syscall;
|
reg sig_trap;
|
reg sig_trap;
|
reg except_illegal;
|
reg except_illegal;
|
| Line 175... |
Line 179... |
reg ex_delayslot_dsi;
|
reg ex_delayslot_dsi;
|
reg ex_delayslot_nop;
|
reg ex_delayslot_nop;
|
reg spr_read;
|
reg spr_read;
|
reg spr_write;
|
reg spr_write;
|
reg [31:2] ex_branch_addrtarget;
|
reg [31:2] ex_branch_addrtarget;
|
|
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
|
|
reg dc_no_writethrough;
|
|
`endif
|
|
|
//
|
//
|
// Register file read addresses
|
// Register file read addresses
|
//
|
//
|
assign rf_addra = if_insn[20:16];
|
assign rf_addra = if_insn[20:16];
|
| Line 209... |
Line 216... |
// next different is DS insn, previous different was Jump/Branch
|
// next different is DS insn, previous different was Jump/Branch
|
// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
|
// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
ex_delayslot_nop <= #1 1'b0;
|
ex_delayslot_nop <= 1'b0;
|
ex_delayslot_dsi <= #1 1'b0;
|
ex_delayslot_dsi <= 1'b0;
|
end
|
end
|
else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
|
else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
|
ex_delayslot_nop <= #1 id_void;
|
ex_delayslot_nop <= id_void;
|
ex_delayslot_dsi <= #1 !id_void;
|
ex_delayslot_dsi <= !id_void;
|
end
|
end
|
else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
|
else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
|
ex_delayslot_nop <= #1 1'b0;
|
ex_delayslot_nop <= 1'b0;
|
ex_delayslot_dsi <= #1 1'b0;
|
ex_delayslot_dsi <= 1'b0;
|
end
|
end
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_delayslot_nop <= #1 id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
ex_delayslot_nop <= id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
ex_delayslot_dsi <= #1 !id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
ex_delayslot_dsi <= !id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
|
(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
(ex_branch_op != `OR1200_BRANCHOP_RFE);
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
| Line 241... |
Line 248... |
//
|
//
|
// EX Sign/Zero extension of immediates
|
// EX Sign/Zero extension of immediates
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
ex_simm <= #1 32'h0000_0000;
|
ex_simm <= 32'h0000_0000;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_simm <= #1 id_simm;
|
ex_simm <= id_simm;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// ID Sign/Zero extension of immediate
|
// ID Sign/Zero extension of immediate
|
| Line 312... |
Line 319... |
//
|
//
|
|
|
// pipeline ID and EX branch target address
|
// pipeline ID and EX branch target address
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
ex_branch_addrtarget <= #1 32'h00000000;
|
ex_branch_addrtarget <= 32'h00000000;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_branch_addrtarget <= #1 id_branch_addrtarget;
|
ex_branch_addrtarget <= id_branch_addrtarget;
|
end
|
end
|
// not pipelined
|
// not pipelined
|
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
|
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
|
|
|
//
|
//
|
| Line 343... |
Line 350... |
// l.macrc in EX stage
|
// l.macrc in EX stage
|
//
|
//
|
`ifdef OR1200_MAC_IMPLEMENTED
|
`ifdef OR1200_MAC_IMPLEMENTED
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
ex_macrc_op <= #1 1'b0;
|
ex_macrc_op <= 1'b0;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
ex_macrc_op <= #1 1'b0;
|
ex_macrc_op <= 1'b0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_macrc_op <= #1 id_macrc_op;
|
ex_macrc_op <= id_macrc_op;
|
end
|
end
|
`else
|
`else
|
assign ex_macrc_op = 1'b0;
|
assign ex_macrc_op = 1'b0;
|
`endif
|
`endif
|
|
|
| Line 443... |
Line 450... |
endcase
|
endcase
|
|
|
`OR1200_OR32_MULI:
|
`OR1200_OR32_MULI:
|
multicycle = 2'h3;
|
multicycle = 2'h3;
|
|
|
`ifdef OR1200_FPU_IMPLEMENTED
|
|
`OR1200_OR32_FLOAT:
|
|
multicycle = `OR1200_FPUOP_CYCLES;
|
|
`endif
|
|
|
|
|
|
// Single cycle instructions
|
// Single cycle instructions
|
default: begin
|
default: begin
|
multicycle = `OR1200_ONE_CYCLE;
|
multicycle = `OR1200_ONE_CYCLE;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
end // always @ (id_insn)
|
|
|
|
//
|
|
// Encode wait_on signal
|
|
//
|
|
always @(id_insn) begin
|
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
`ifdef OR1200_FPU_IMPLEMENTED
|
|
`OR1200_OR32_FLOAT: begin
|
|
wait_on = id_insn[`OR1200_FPUOP_DOUBLE_BIT] ? 0 : `OR1200_WAIT_ON_FPU;
|
end
|
end
|
|
`endif
|
|
`ifndef OR1200_DC_WRITHROUGH
|
|
// l.mtspr
|
|
`OR1200_OR32_MTSPR: begin
|
|
wait_on = `OR1200_WAIT_ON_MTSPR;
|
|
end
|
|
`endif
|
|
default: begin
|
|
wait_on = 0;
|
|
end
|
|
endcase // case (id_insn[31:26])
|
|
end // always @ (id_insn)
|
|
|
|
|
|
|
|
|
//
|
//
|
// Register file write address
|
// Register file write address
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
rf_addrw <= #1 5'd0;
|
rf_addrw <= 5'd0;
|
else if (!ex_freeze & id_freeze)
|
else if (!ex_freeze & id_freeze)
|
rf_addrw <= #1 5'd00;
|
rf_addrw <= 5'd00;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
`OR1200_OR32_JAL, `OR1200_OR32_JALR:
|
`OR1200_OR32_JAL, `OR1200_OR32_JALR:
|
rf_addrw <= #1 5'd09; // link register r9
|
rf_addrw <= 5'd09; // link register r9
|
default:
|
default:
|
rf_addrw <= #1 id_insn[25:21];
|
rf_addrw <= id_insn[25:21];
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// rf_addrw in wb stage (used in forwarding logic)
|
// rf_addrw in wb stage (used in forwarding logic)
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
wb_rfaddrw <= #1 5'd0;
|
wb_rfaddrw <= 5'd0;
|
else if (!wb_freeze)
|
else if (!wb_freeze)
|
wb_rfaddrw <= #1 rf_addrw;
|
wb_rfaddrw <= rf_addrw;
|
end
|
end
|
|
|
//
|
//
|
// Instruction latch in id_insn
|
// Instruction latch in id_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (id_flushpipe)
|
else if (id_flushpipe)
|
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> id_insn[16] must be 1
|
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> id_insn[16] must be 1
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
id_insn <= #1 if_insn;
|
id_insn <= if_insn;
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: id_insn <= %h", $time, if_insn);
|
$display("%t: id_insn <= %h", $time, if_insn);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
| Line 507... |
Line 532... |
//
|
//
|
// Instruction latch in ex_insn
|
// Instruction latch in ex_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> ex_insn[16] must be 1
|
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> ex_insn[16] must be 1
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_insn <= #1 id_insn;
|
ex_insn <= id_insn;
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: ex_insn <= %h", $time, id_insn);
|
$display("%t: ex_insn <= %h", $time, id_insn);
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
| Line 525... |
Line 550... |
//
|
//
|
// Instruction latch in wb_insn
|
// Instruction latch in wb_insn
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
|
wb_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
|
// wb_insn should not be changed by exceptions due to correct
|
// wb_insn should not be changed by exceptions due to correct
|
// recording of display_arch_state in the or1200_monitor!
|
// recording of display_arch_state in the or1200_monitor!
|
// wb_insn changed by exception is not used elsewhere!
|
// wb_insn changed by exception is not used elsewhere!
|
else if (!wb_freeze) begin
|
else if (!wb_freeze) begin
|
wb_insn <= #1 ex_insn;
|
wb_insn <= ex_insn;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Decode of sel_imm
|
// Decode of sel_imm
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
case (if_insn[31:26]) // synopsys parallel_case
|
case (if_insn[31:26]) // synopsys parallel_case
|
|
|
// j.jalr
|
// j.jalr
|
`OR1200_OR32_JALR:
|
`OR1200_OR32_JALR:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// l.jr
|
// l.jr
|
`OR1200_OR32_JR:
|
`OR1200_OR32_JR:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// l.rfe
|
// l.rfe
|
`OR1200_OR32_RFE:
|
`OR1200_OR32_RFE:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// l.mfspr
|
// l.mfspr
|
`OR1200_OR32_MFSPR:
|
`OR1200_OR32_MFSPR:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// l.mtspr
|
// l.mtspr
|
`OR1200_OR32_MTSPR:
|
`OR1200_OR32_MTSPR:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// l.sys, l.brk and all three sync insns
|
// l.sys, l.brk and all three sync insns
|
`OR1200_OR32_XSYNC:
|
`OR1200_OR32_XSYNC:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// l.mac/l.msb
|
// l.mac/l.msb
|
`ifdef OR1200_MAC_IMPLEMENTED
|
`ifdef OR1200_MAC_IMPLEMENTED
|
`OR1200_OR32_MACMSB:
|
`OR1200_OR32_MACMSB:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
`endif
|
`endif
|
|
|
// l.sw
|
// l.sw
|
`OR1200_OR32_SW:
|
`OR1200_OR32_SW:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// l.sb
|
// l.sb
|
`OR1200_OR32_SB:
|
`OR1200_OR32_SB:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// l.sh
|
// l.sh
|
`OR1200_OR32_SH:
|
`OR1200_OR32_SH:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// ALU instructions except the one with immediate
|
// ALU instructions except the one with immediate
|
`OR1200_OR32_ALU:
|
`OR1200_OR32_ALU:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// SFXX instructions
|
// SFXX instructions
|
`OR1200_OR32_SFXX:
|
`OR1200_OR32_SFXX:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
`ifdef OR1200_OR32_CUST5
|
`ifdef OR1200_OR32_CUST5
|
// l.cust5 instructions
|
// l.cust5 instructions
|
`OR1200_OR32_CUST5:
|
`OR1200_OR32_CUST5:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
`endif
|
`endif
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`ifdef OR1200_FPU_IMPLEMENTED
|
// FPU instructions
|
// FPU instructions
|
`OR1200_OR32_FLOAT:
|
`OR1200_OR32_FLOAT:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
`endif
|
`endif
|
// l.nop
|
// l.nop
|
`OR1200_OR32_NOP:
|
`OR1200_OR32_NOP:
|
sel_imm <= #1 1'b0;
|
sel_imm <= 1'b0;
|
|
|
// All instructions with immediates
|
// All instructions with immediates
|
default: begin
|
default: begin
|
sel_imm <= #1 1'b1;
|
sel_imm <= 1'b1;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
| Line 622... |
Line 647... |
//
|
//
|
// Decode of except_illegal
|
// Decode of except_illegal
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
except_illegal <= #1 1'b0;
|
except_illegal <= 1'b0;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
except_illegal <= #1 1'b0;
|
except_illegal <= 1'b0;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
`OR1200_OR32_J,
|
`OR1200_OR32_J,
|
`OR1200_OR32_JAL,
|
`OR1200_OR32_JAL,
|
| Line 668... |
Line 693... |
`OR1200_OR32_SFXX,
|
`OR1200_OR32_SFXX,
|
`ifdef OR1200_OR32_CUST5
|
`ifdef OR1200_OR32_CUST5
|
`OR1200_OR32_CUST5,
|
`OR1200_OR32_CUST5,
|
`endif
|
`endif
|
`OR1200_OR32_NOP:
|
`OR1200_OR32_NOP:
|
except_illegal <= #1 1'b0;
|
except_illegal <= 1'b0;
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`OR1200_OR32_FLOAT:
|
`OR1200_OR32_FLOAT:
|
// Check it's not a double precision instruction
|
// Check it's not a double precision instruction
|
except_illegal <= #1 id_insn[`OR1200_FPUOP_DOUBLE_BIT];
|
except_illegal <= id_insn[`OR1200_FPUOP_DOUBLE_BIT];
|
`endif
|
`endif
|
|
|
`OR1200_OR32_ALU:
|
`OR1200_OR32_ALU:
|
except_illegal <= #1 1'b0
|
except_illegal <= 1'b0
|
|
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_IMPL_DIV
|
`ifdef OR1200_DIV_IMPLEMENTED
|
`else
|
`else
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
|
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
|
`endif
|
`endif
|
`else
|
`else
|
| Line 708... |
Line 733... |
`endif
|
`endif
|
;
|
;
|
|
|
// Illegal and OR1200 unsupported instructions
|
// Illegal and OR1200 unsupported instructions
|
default:
|
default:
|
except_illegal <= #1 1'b1;
|
except_illegal <= 1'b1;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
end
|
end
|
| Line 720... |
Line 745... |
//
|
//
|
// Decode of alu_op
|
// Decode of alu_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
alu_op <= #1 `OR1200_ALUOP_NOP;
|
alu_op <= `OR1200_ALUOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
alu_op <= #1 `OR1200_ALUOP_NOP;
|
alu_op <= `OR1200_ALUOP_NOP;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
// l.movhi
|
// l.movhi
|
`OR1200_OR32_MOVHI:
|
`OR1200_OR32_MOVHI:
|
alu_op <= #1 `OR1200_ALUOP_MOVHI;
|
alu_op <= `OR1200_ALUOP_MOVHI;
|
|
|
// l.addi
|
// l.addi
|
`OR1200_OR32_ADDI:
|
`OR1200_OR32_ADDI:
|
alu_op <= #1 `OR1200_ALUOP_ADD;
|
alu_op <= `OR1200_ALUOP_ADD;
|
|
|
// l.addic
|
// l.addic
|
`OR1200_OR32_ADDIC:
|
`OR1200_OR32_ADDIC:
|
alu_op <= #1 `OR1200_ALUOP_ADDC;
|
alu_op <= `OR1200_ALUOP_ADDC;
|
|
|
// l.andi
|
// l.andi
|
`OR1200_OR32_ANDI:
|
`OR1200_OR32_ANDI:
|
alu_op <= #1 `OR1200_ALUOP_AND;
|
alu_op <= `OR1200_ALUOP_AND;
|
|
|
// l.ori
|
// l.ori
|
`OR1200_OR32_ORI:
|
`OR1200_OR32_ORI:
|
alu_op <= #1 `OR1200_ALUOP_OR;
|
alu_op <= `OR1200_ALUOP_OR;
|
|
|
// l.xori
|
// l.xori
|
`OR1200_OR32_XORI:
|
`OR1200_OR32_XORI:
|
alu_op <= #1 `OR1200_ALUOP_XOR;
|
alu_op <= `OR1200_ALUOP_XOR;
|
|
|
// l.muli
|
// l.muli
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`OR1200_OR32_MULI:
|
`OR1200_OR32_MULI:
|
alu_op <= #1 `OR1200_ALUOP_MUL;
|
alu_op <= `OR1200_ALUOP_MUL;
|
`endif
|
`endif
|
|
|
// Shift and rotate insns with immediate
|
// Shift and rotate insns with immediate
|
`OR1200_OR32_SH_ROTI:
|
`OR1200_OR32_SH_ROTI:
|
alu_op <= #1 `OR1200_ALUOP_SHROT;
|
alu_op <= `OR1200_ALUOP_SHROT;
|
|
|
// SFXX insns with immediate
|
// SFXX insns with immediate
|
`OR1200_OR32_SFXXI:
|
`OR1200_OR32_SFXXI:
|
alu_op <= #1 `OR1200_ALUOP_COMP;
|
alu_op <= `OR1200_ALUOP_COMP;
|
|
|
// ALU instructions except the one with immediate
|
// ALU instructions except the one with immediate
|
`OR1200_OR32_ALU:
|
`OR1200_OR32_ALU:
|
alu_op <= #1 id_insn[3:0];
|
alu_op <= id_insn[3:0];
|
|
|
// SFXX instructions
|
// SFXX instructions
|
`OR1200_OR32_SFXX:
|
`OR1200_OR32_SFXX:
|
alu_op <= #1 `OR1200_ALUOP_COMP;
|
alu_op <= `OR1200_ALUOP_COMP;
|
|
|
`ifdef OR1200_OR32_CUST5
|
`ifdef OR1200_OR32_CUST5
|
// l.cust5 instructions
|
// l.cust5 instructions
|
`OR1200_OR32_CUST5:
|
`OR1200_OR32_CUST5:
|
alu_op <= #1 `OR1200_ALUOP_CUST5;
|
alu_op <= `OR1200_ALUOP_CUST5;
|
`endif
|
`endif
|
|
|
// Default
|
// Default
|
default: begin
|
default: begin
|
alu_op <= #1 `OR1200_ALUOP_NOP;
|
alu_op <= `OR1200_ALUOP_NOP;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
| Line 793... |
Line 818... |
//
|
//
|
// Decode of spr_read, spr_write
|
// Decode of spr_read, spr_write
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
spr_read <= #1 1'b0;
|
spr_read <= 1'b0;
|
spr_write <= #1 1'b0;
|
spr_write <= 1'b0;
|
end
|
end
|
else if (!ex_freeze & id_freeze | ex_flushpipe) begin
|
else if (!ex_freeze & id_freeze | ex_flushpipe) begin
|
spr_read <= #1 1'b0;
|
spr_read <= 1'b0;
|
spr_write <= #1 1'b0;
|
spr_write <= 1'b0;
|
end
|
end
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
// l.mfspr
|
// l.mfspr
|
`OR1200_OR32_MFSPR: begin
|
`OR1200_OR32_MFSPR: begin
|
spr_read <= #1 1'b1;
|
spr_read <= 1'b1;
|
spr_write <= #1 1'b0;
|
spr_write <= 1'b0;
|
end
|
end
|
|
|
// l.mtspr
|
// l.mtspr
|
`OR1200_OR32_MTSPR: begin
|
`OR1200_OR32_MTSPR: begin
|
spr_read <= #1 1'b0;
|
spr_read <= 1'b0;
|
spr_write <= #1 1'b1;
|
spr_write <= 1'b1;
|
end
|
end
|
|
|
// Default
|
// Default
|
default: begin
|
default: begin
|
spr_read <= #1 1'b0;
|
spr_read <= 1'b0;
|
spr_write <= #1 1'b0;
|
spr_write <= 1'b0;
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
| Line 834... |
Line 859... |
always @(id_insn) begin
|
always @(id_insn) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
// l.maci
|
// l.maci
|
`OR1200_OR32_MACI:
|
`OR1200_OR32_MACI:
|
id_mac_op <= #1 `OR1200_MACOP_MAC;
|
id_mac_op <= `OR1200_MACOP_MAC;
|
|
|
// l.mac, l.msb
|
// l.mac, l.msb
|
`OR1200_OR32_MACMSB:
|
`OR1200_OR32_MACMSB:
|
id_mac_op <= #1 id_insn[2:0];
|
id_mac_op <= id_insn[2:0];
|
|
|
// Illegal and OR1200 unsupported instructions
|
// Illegal and OR1200 unsupported instructions
|
default:
|
default:
|
id_mac_op <= #1 `OR1200_MACOP_NOP;
|
id_mac_op <= `OR1200_MACOP_NOP;
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
ex_mac_op <= #1 `OR1200_MACOP_NOP;
|
ex_mac_op <= `OR1200_MACOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
ex_mac_op <= #1 `OR1200_MACOP_NOP;
|
ex_mac_op <= `OR1200_MACOP_NOP;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_mac_op <= #1 id_mac_op;
|
ex_mac_op <= id_mac_op;
|
end
|
end
|
|
|
assign mac_op = abort_mvspr ? `OR1200_MACOP_NOP : ex_mac_op;
|
assign mac_op = abort_mvspr ? `OR1200_MACOP_NOP : ex_mac_op;
|
`else
|
`else
|
assign id_mac_op = `OR1200_MACOP_NOP;
|
assign id_mac_op = `OR1200_MACOP_NOP;
|
| Line 867... |
Line 892... |
//
|
//
|
// Decode of shrot_op
|
// Decode of shrot_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
shrot_op <= #1 `OR1200_SHROTOP_NOP;
|
shrot_op <= `OR1200_SHROTOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
shrot_op <= #1 `OR1200_SHROTOP_NOP;
|
shrot_op <= `OR1200_SHROTOP_NOP;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
shrot_op <= #1 id_insn[`OR1200_SHROTOP_POS];
|
shrot_op <= id_insn[`OR1200_SHROTOP_POS];
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Decode of rfwb_op
|
// Decode of rfwb_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
|
rfwb_op <= `OR1200_RFWBOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
|
rfwb_op <= `OR1200_RFWBOP_NOP;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
// j.jal
|
// j.jal
|
`OR1200_OR32_JAL:
|
`OR1200_OR32_JAL:
|
rfwb_op <= #1 {`OR1200_RFWBOP_LR, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_LR, 1'b1};
|
|
|
// j.jalr
|
// j.jalr
|
`OR1200_OR32_JALR:
|
`OR1200_OR32_JALR:
|
rfwb_op <= #1 {`OR1200_RFWBOP_LR, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_LR, 1'b1};
|
|
|
// l.movhi
|
// l.movhi
|
`OR1200_OR32_MOVHI:
|
`OR1200_OR32_MOVHI:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
|
|
// l.mfspr
|
// l.mfspr
|
`OR1200_OR32_MFSPR:
|
`OR1200_OR32_MFSPR:
|
rfwb_op <= #1 {`OR1200_RFWBOP_SPRS, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_SPRS, 1'b1};
|
|
|
// l.lwz
|
// l.lwz
|
`OR1200_OR32_LWZ:
|
`OR1200_OR32_LWZ:
|
rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
|
|
|
// l.lbz
|
// l.lbz
|
`OR1200_OR32_LBZ:
|
`OR1200_OR32_LBZ:
|
rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
|
|
|
// l.lbs
|
// l.lbs
|
`OR1200_OR32_LBS:
|
`OR1200_OR32_LBS:
|
rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
|
|
|
// l.lhz
|
// l.lhz
|
`OR1200_OR32_LHZ:
|
`OR1200_OR32_LHZ:
|
rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
|
|
|
// l.lhs
|
// l.lhs
|
`OR1200_OR32_LHS:
|
`OR1200_OR32_LHS:
|
rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
|
|
|
// l.addi
|
// l.addi
|
`OR1200_OR32_ADDI:
|
`OR1200_OR32_ADDI:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
|
|
// l.addic
|
// l.addic
|
`OR1200_OR32_ADDIC:
|
`OR1200_OR32_ADDIC:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
|
|
// l.andi
|
// l.andi
|
`OR1200_OR32_ANDI:
|
`OR1200_OR32_ANDI:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
|
|
// l.ori
|
// l.ori
|
`OR1200_OR32_ORI:
|
`OR1200_OR32_ORI:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
|
|
// l.xori
|
// l.xori
|
`OR1200_OR32_XORI:
|
`OR1200_OR32_XORI:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
|
|
// l.muli
|
// l.muli
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`OR1200_OR32_MULI:
|
`OR1200_OR32_MULI:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
`endif
|
`endif
|
|
|
// Shift and rotate insns with immediate
|
// Shift and rotate insns with immediate
|
`OR1200_OR32_SH_ROTI:
|
`OR1200_OR32_SH_ROTI:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
|
|
// ALU instructions except the one with immediate
|
// ALU instructions except the one with immediate
|
`OR1200_OR32_ALU:
|
`OR1200_OR32_ALU:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
|
|
`ifdef OR1200_OR32_CUST5
|
`ifdef OR1200_OR32_CUST5
|
// l.cust5 instructions
|
// l.cust5 instructions
|
`OR1200_OR32_CUST5:
|
`OR1200_OR32_CUST5:
|
rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
|
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
|
`endif
|
`endif
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`ifdef OR1200_FPU_IMPLEMENTED
|
// FPU instructions, lf.XXX.s, except sfxx
|
// FPU instructions, lf.XXX.s, except sfxx
|
`OR1200_OR32_FLOAT:
|
`OR1200_OR32_FLOAT:
|
rfwb_op <= #1 {`OR1200_RFWBOP_FPU,!id_insn[3]};
|
rfwb_op <= {`OR1200_RFWBOP_FPU,!id_insn[3]};
|
`endif
|
`endif
|
// Instructions w/o register-file write-back
|
// Instructions w/o register-file write-back
|
default:
|
default:
|
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
|
rfwb_op <= `OR1200_RFWBOP_NOP;
|
|
|
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
| Line 980... |
Line 1005... |
//
|
//
|
// Decode of id_branch_op
|
// Decode of id_branch_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
id_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
id_branch_op <= `OR1200_BRANCHOP_NOP;
|
else if (id_flushpipe)
|
else if (id_flushpipe)
|
id_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
id_branch_op <= `OR1200_BRANCHOP_NOP;
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
case (if_insn[31:26]) // synopsys parallel_case
|
case (if_insn[31:26]) // synopsys parallel_case
|
|
|
// l.j
|
// l.j
|
`OR1200_OR32_J:
|
`OR1200_OR32_J:
|
id_branch_op <= #1 `OR1200_BRANCHOP_J;
|
id_branch_op <= `OR1200_BRANCHOP_J;
|
|
|
// j.jal
|
// j.jal
|
`OR1200_OR32_JAL:
|
`OR1200_OR32_JAL:
|
id_branch_op <= #1 `OR1200_BRANCHOP_J;
|
id_branch_op <= `OR1200_BRANCHOP_J;
|
|
|
// j.jalr
|
// j.jalr
|
`OR1200_OR32_JALR:
|
`OR1200_OR32_JALR:
|
id_branch_op <= #1 `OR1200_BRANCHOP_JR;
|
id_branch_op <= `OR1200_BRANCHOP_JR;
|
|
|
// l.jr
|
// l.jr
|
`OR1200_OR32_JR:
|
`OR1200_OR32_JR:
|
id_branch_op <= #1 `OR1200_BRANCHOP_JR;
|
id_branch_op <= `OR1200_BRANCHOP_JR;
|
|
|
// l.bnf
|
// l.bnf
|
`OR1200_OR32_BNF:
|
`OR1200_OR32_BNF:
|
id_branch_op <= #1 `OR1200_BRANCHOP_BNF;
|
id_branch_op <= `OR1200_BRANCHOP_BNF;
|
|
|
// l.bf
|
// l.bf
|
`OR1200_OR32_BF:
|
`OR1200_OR32_BF:
|
id_branch_op <= #1 `OR1200_BRANCHOP_BF;
|
id_branch_op <= `OR1200_BRANCHOP_BF;
|
|
|
// l.rfe
|
// l.rfe
|
`OR1200_OR32_RFE:
|
`OR1200_OR32_RFE:
|
id_branch_op <= #1 `OR1200_BRANCHOP_RFE;
|
id_branch_op <= `OR1200_BRANCHOP_RFE;
|
|
|
// Non branch instructions
|
// Non branch instructions
|
default:
|
default:
|
id_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
id_branch_op <= `OR1200_BRANCHOP_NOP;
|
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Generation of ex_branch_op
|
// Generation of ex_branch_op
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
ex_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
ex_branch_op <= `OR1200_BRANCHOP_NOP;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
ex_branch_op <= #1 `OR1200_BRANCHOP_NOP;
|
ex_branch_op <= `OR1200_BRANCHOP_NOP;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
ex_branch_op <= #1 id_branch_op;
|
ex_branch_op <= id_branch_op;
|
|
|
//
|
//
|
// Decode of id_lsu_op
|
// Decode of id_lsu_op
|
//
|
//
|
always @(id_insn) begin
|
always @(id_insn) begin
|
case (id_insn[31:26]) // synopsys parallel_case
|
case (id_insn[31:26]) // synopsys parallel_case
|
|
|
// l.lwz
|
// l.lwz
|
`OR1200_OR32_LWZ:
|
`OR1200_OR32_LWZ:
|
id_lsu_op <= #1 `OR1200_LSUOP_LWZ;
|
id_lsu_op <= `OR1200_LSUOP_LWZ;
|
|
|
// l.lbz
|
// l.lbz
|
`OR1200_OR32_LBZ:
|
`OR1200_OR32_LBZ:
|
id_lsu_op <= #1 `OR1200_LSUOP_LBZ;
|
id_lsu_op <= `OR1200_LSUOP_LBZ;
|
|
|
// l.lbs
|
// l.lbs
|
`OR1200_OR32_LBS:
|
`OR1200_OR32_LBS:
|
id_lsu_op <= #1 `OR1200_LSUOP_LBS;
|
id_lsu_op <= `OR1200_LSUOP_LBS;
|
|
|
// l.lhz
|
// l.lhz
|
`OR1200_OR32_LHZ:
|
`OR1200_OR32_LHZ:
|
id_lsu_op <= #1 `OR1200_LSUOP_LHZ;
|
id_lsu_op <= `OR1200_LSUOP_LHZ;
|
|
|
// l.lhs
|
// l.lhs
|
`OR1200_OR32_LHS:
|
`OR1200_OR32_LHS:
|
id_lsu_op <= #1 `OR1200_LSUOP_LHS;
|
id_lsu_op <= `OR1200_LSUOP_LHS;
|
|
|
// l.sw
|
// l.sw
|
`OR1200_OR32_SW:
|
`OR1200_OR32_SW:
|
id_lsu_op <= #1 `OR1200_LSUOP_SW;
|
id_lsu_op <= `OR1200_LSUOP_SW;
|
|
|
// l.sb
|
// l.sb
|
`OR1200_OR32_SB:
|
`OR1200_OR32_SB:
|
id_lsu_op <= #1 `OR1200_LSUOP_SB;
|
id_lsu_op <= `OR1200_LSUOP_SB;
|
|
|
// l.sh
|
// l.sh
|
`OR1200_OR32_SH:
|
`OR1200_OR32_SH:
|
id_lsu_op <= #1 `OR1200_LSUOP_SH;
|
id_lsu_op <= `OR1200_LSUOP_SH;
|
|
|
// Non load/store instructions
|
// Non load/store instructions
|
default:
|
default:
|
id_lsu_op <= #1 `OR1200_LSUOP_NOP;
|
id_lsu_op <= `OR1200_LSUOP_NOP;
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Decode of comp_op
|
// Decode of comp_op
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
comp_op <= #1 4'd0;
|
comp_op <= 4'd0;
|
end else if (!ex_freeze & id_freeze | ex_flushpipe)
|
end else if (!ex_freeze & id_freeze | ex_flushpipe)
|
comp_op <= #1 4'd0;
|
comp_op <= 4'd0;
|
else if (!ex_freeze)
|
else if (!ex_freeze)
|
comp_op <= #1 id_insn[24:21];
|
comp_op <= id_insn[24:21];
|
end
|
end
|
|
|
`ifdef OR1200_FPU_IMPLEMENTED
|
`ifdef OR1200_FPU_IMPLEMENTED
|
//
|
//
|
// Decode of FPU ops
|
// Decode of FPU ops
|
//
|
//
|
assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT), id_insn[`OR1200_FPUOP_WIDTH-2:0]};
|
assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT),
|
|
id_insn[`OR1200_FPUOP_WIDTH-2:0]};
|
`else
|
`else
|
assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}};
|
assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}};
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// Decode of l.sys
|
// Decode of l.sys
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
sig_syscall <= #1 1'b0;
|
sig_syscall <= 1'b0;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
sig_syscall <= #1 1'b0;
|
sig_syscall <= 1'b0;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
|
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
|
$display("Generating sig_syscall");
|
$display("Generating sig_syscall");
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
sig_syscall <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
|
sig_syscall <= (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Decode of l.trap
|
// Decode of l.trap
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst)
|
if (rst)
|
sig_trap <= #1 1'b0;
|
sig_trap <= 1'b0;
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
else if (!ex_freeze & id_freeze | ex_flushpipe)
|
sig_trap <= #1 1'b0;
|
sig_trap <= 1'b0;
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
|
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
|
$display("Generating sig_trap");
|
$display("Generating sig_trap");
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
sig_trap <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
|
sig_trap <= (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
|
| du_hwbkpt;
|
| du_hwbkpt;
|
end
|
end
|
end
|
end
|
|
|
|
// Decode destination register address for data cache to check if store ops
|
|
// are being done from the stack register (r1) or frame pointer register (r2)
|
|
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst)
|
|
dc_no_writethrough <= 0;
|
|
else if (!ex_freeze)
|
|
dc_no_writethrough <= (id_insn[20:16] == 5'd1) | (id_insn[20:16] == 5'd2);
|
|
end
|
|
`else
|
|
|
|
assign dc_no_writethrough = 0;
|
|
|
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
