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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Diff between revs 258 and 353

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Rev 258 Rev 353
Line 77... Line 77...
// I/O
// I/O
//
//
input                                   clk;
input                                   clk;
input                                   rst;
input                                   rst;
input                                   id_freeze;
input                                   id_freeze;
input                                   ex_freeze;
input                                   ex_freeze /* verilator public */;
input                                   wb_freeze;
input                                   wb_freeze /* verilator public */;
output                                  if_flushpipe;
output                                  if_flushpipe;
output                                  id_flushpipe;
output                                  id_flushpipe;
output                                  ex_flushpipe;
output                                  ex_flushpipe;
output                                  wb_flushpipe;
output                                  wb_flushpipe;
input                                   extend_flush;
input                                   extend_flush;
input                                   except_flushpipe;
input                                   except_flushpipe;
input                           abort_mvspr ;
input                           abort_mvspr ;
input   [31:0]                   if_insn;
input   [31:0]                   if_insn;
output  [31:0]                   id_insn;
output  [31:0]                   id_insn;
output  [31:0]                   ex_insn;
output  [31:0]                   ex_insn /* verilator public */;
output  [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
output  [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
output  [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
output  [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
input                                           ex_branch_taken;
input                                           ex_branch_taken;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
Line 153... Line 153...
`else
`else
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
wire                                    ex_macrc_op;
wire                                    ex_macrc_op;
`endif
`endif
reg     [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
reg     [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
reg     [31:0]                           id_insn;
reg     [31:0]                           id_insn /* verilator public */;
reg     [31:0]                           ex_insn;
reg     [31:0]                           ex_insn /* verilator public */;
reg     [31:0]                           wb_insn;
reg     [31:0]                           wb_insn /* verilator public */;
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
reg     [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
reg     [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
reg     [`OR1200_SEL_WIDTH-1:0]          sel_a;
reg     [`OR1200_SEL_WIDTH-1:0]          sel_a;
reg     [`OR1200_SEL_WIDTH-1:0]          sel_b;
reg     [`OR1200_SEL_WIDTH-1:0]          sel_b;
Line 371... Line 371...
//
//
//
//
//
//
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
 
 
 
 
 
`ifdef verilator
 
   // Function to access wb_insn (for Verilator). Have to hide this from
 
   // simulator, since functions with no inputs are not allowed in IEEE
 
   // 1364-2001.
 
   function [31:0] get_wb_insn;
 
      // verilator public
 
      get_wb_insn = wb_insn;
 
   endfunction // get_wb_insn
 
 
 
   // Function to access id_insn (for Verilator). Have to hide this from
 
   // simulator, since functions with no inputs are not allowed in IEEE
 
   // 1364-2001.
 
   function [31:0] get_id_insn;
 
      // verilator public
 
      get_id_insn = id_insn;
 
   endfunction // get_id_insn
 
 
 
   // Function to access ex_insn (for Verilator). Have to hide this from
 
   // simulator, since functions with no inputs are not allowed in IEEE
 
   // 1364-2001.
 
   function [31:0] get_ex_insn;
 
      // verilator public
 
      get_ex_insn = ex_insn;
 
   endfunction // get_ex_insn
 
 
 
`endif
 
 
 
 
//
//
// Generation of sel_a
// Generation of sel_a
//
//
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
Line 859... Line 888...
always @(id_insn) begin
always @(id_insn) begin
        case (id_insn[31:26])           // synopsys parallel_case
        case (id_insn[31:26])           // synopsys parallel_case
 
 
        // l.maci
        // l.maci
        `OR1200_OR32_MACI:
        `OR1200_OR32_MACI:
                id_mac_op <=  `OR1200_MACOP_MAC;
                id_mac_op =  `OR1200_MACOP_MAC;
 
 
        // l.mac, l.msb
        // l.mac, l.msb
        `OR1200_OR32_MACMSB:
        `OR1200_OR32_MACMSB:
                id_mac_op <=  id_insn[2:0];
                id_mac_op =  id_insn[2:0];
 
 
        // Illegal and OR1200 unsupported instructions
        // Illegal and OR1200 unsupported instructions
        default:
        default:
                id_mac_op <=  `OR1200_MACOP_NOP;
                id_mac_op =  `OR1200_MACOP_NOP;
 
 
        endcase
        endcase
end
end
 
 
always @(posedge clk or posedge rst) begin
always @(posedge clk or posedge rst) begin
Line 1066... Line 1095...
always @(id_insn) begin
always @(id_insn) begin
        case (id_insn[31:26])           // synopsys parallel_case
        case (id_insn[31:26])           // synopsys parallel_case
 
 
        // l.lwz
        // l.lwz
        `OR1200_OR32_LWZ:
        `OR1200_OR32_LWZ:
                id_lsu_op <=  `OR1200_LSUOP_LWZ;
                id_lsu_op =  `OR1200_LSUOP_LWZ;
 
 
        // l.lbz
        // l.lbz
        `OR1200_OR32_LBZ:
        `OR1200_OR32_LBZ:
                id_lsu_op <=  `OR1200_LSUOP_LBZ;
                id_lsu_op =  `OR1200_LSUOP_LBZ;
 
 
        // l.lbs
        // l.lbs
        `OR1200_OR32_LBS:
        `OR1200_OR32_LBS:
                id_lsu_op <=  `OR1200_LSUOP_LBS;
                id_lsu_op =  `OR1200_LSUOP_LBS;
 
 
        // l.lhz
        // l.lhz
        `OR1200_OR32_LHZ:
        `OR1200_OR32_LHZ:
                id_lsu_op <=  `OR1200_LSUOP_LHZ;
                id_lsu_op =  `OR1200_LSUOP_LHZ;
 
 
        // l.lhs
        // l.lhs
        `OR1200_OR32_LHS:
        `OR1200_OR32_LHS:
                id_lsu_op <=  `OR1200_LSUOP_LHS;
                id_lsu_op =  `OR1200_LSUOP_LHS;
 
 
        // l.sw
        // l.sw
        `OR1200_OR32_SW:
        `OR1200_OR32_SW:
                id_lsu_op <=  `OR1200_LSUOP_SW;
                id_lsu_op =  `OR1200_LSUOP_SW;
 
 
        // l.sb
        // l.sb
        `OR1200_OR32_SB:
        `OR1200_OR32_SB:
                id_lsu_op <=  `OR1200_LSUOP_SB;
                id_lsu_op =  `OR1200_LSUOP_SB;
 
 
        // l.sh
        // l.sh
        `OR1200_OR32_SH:
        `OR1200_OR32_SH:
                id_lsu_op <=  `OR1200_LSUOP_SH;
                id_lsu_op =  `OR1200_LSUOP_SH;
 
 
        // Non load/store instructions
        // Non load/store instructions
        default:
        default:
                id_lsu_op <=  `OR1200_LSUOP_NOP;
                id_lsu_op =  `OR1200_LSUOP_NOP;
 
 
        endcase
        endcase
end
end
 
 
//
//

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