| Line 888... |
Line 888... |
else if (!ex_freeze) begin
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys parallel_case
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case (id_insn[31:26]) // synopsys parallel_case
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// j.jal
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// j.jal
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`OR1200_OR32_JAL:
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`OR1200_OR32_JAL:
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rfwb_op <= #1 `OR1200_RFWBOP_LR;
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rfwb_op <= #1 {`OR1200_RFWBOP_LR, 1'b1};
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// j.jalr
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// j.jalr
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`OR1200_OR32_JALR:
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`OR1200_OR32_JALR:
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rfwb_op <= #1 `OR1200_RFWBOP_LR;
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rfwb_op <= #1 {`OR1200_RFWBOP_LR, 1'b1};
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// l.movhi
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// l.movhi
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`OR1200_OR32_MOVHI:
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`OR1200_OR32_MOVHI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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// l.mfspr
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// l.mfspr
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`OR1200_OR32_MFSPR:
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`OR1200_OR32_MFSPR:
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rfwb_op <= #1 `OR1200_RFWBOP_SPRS;
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rfwb_op <= #1 {`OR1200_RFWBOP_SPRS, 1'b1};
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// l.lwz
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// l.lwz
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`OR1200_OR32_LWZ:
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`OR1200_OR32_LWZ:
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rfwb_op <= #1 `OR1200_RFWBOP_LSU;
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rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
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// l.lbz
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// l.lbz
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`OR1200_OR32_LBZ:
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`OR1200_OR32_LBZ:
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rfwb_op <= #1 `OR1200_RFWBOP_LSU;
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rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
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// l.lbs
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// l.lbs
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`OR1200_OR32_LBS:
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`OR1200_OR32_LBS:
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rfwb_op <= #1 `OR1200_RFWBOP_LSU;
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rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
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// l.lhz
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// l.lhz
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`OR1200_OR32_LHZ:
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`OR1200_OR32_LHZ:
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rfwb_op <= #1 `OR1200_RFWBOP_LSU;
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rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
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// l.lhs
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// l.lhs
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`OR1200_OR32_LHS:
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`OR1200_OR32_LHS:
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rfwb_op <= #1 `OR1200_RFWBOP_LSU;
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rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
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// l.addi
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// l.addi
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`OR1200_OR32_ADDI:
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`OR1200_OR32_ADDI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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// l.addic
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// l.addic
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`OR1200_OR32_ADDIC:
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`OR1200_OR32_ADDIC:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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// l.andi
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// l.andi
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`OR1200_OR32_ANDI:
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`OR1200_OR32_ANDI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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// l.ori
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// l.ori
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`OR1200_OR32_ORI:
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`OR1200_OR32_ORI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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// l.xori
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// l.xori
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`OR1200_OR32_XORI:
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`OR1200_OR32_XORI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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// l.muli
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// l.muli
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`ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MULT_IMPLEMENTED
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`OR1200_OR32_MULI:
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`OR1200_OR32_MULI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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`endif
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`endif
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// Shift and rotate insns with immediate
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// Shift and rotate insns with immediate
|
`OR1200_OR32_SH_ROTI:
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`OR1200_OR32_SH_ROTI:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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|
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// ALU instructions except the one with immediate
|
// ALU instructions except the one with immediate
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`OR1200_OR32_ALU:
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`OR1200_OR32_ALU:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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`ifdef OR1200_OR32_CUST5
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`ifdef OR1200_OR32_CUST5
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// l.cust5 instructions
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// l.cust5 instructions
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`OR1200_OR32_CUST5:
|
`OR1200_OR32_CUST5:
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rfwb_op <= #1 `OR1200_RFWBOP_ALU;
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rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
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`endif
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`endif
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`ifdef OR1200_FPU_IMPLEMENTED
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`ifdef OR1200_FPU_IMPLEMENTED
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// FPU instructions, lf.XXX.s, except sfxx
|
// FPU instructions, lf.XXX.s, except sfxx
|
`OR1200_OR32_FLOAT:
|
`OR1200_OR32_FLOAT:
|
rfwb_op <= #1 {`OR1200_RFWBOP_FPU,!id_insn[3]};
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rfwb_op <= #1 {`OR1200_RFWBOP_FPU,!id_insn[3]};
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