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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Diff between revs 185 and 186

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Rev 185 Rev 186
Line 888... Line 888...
        else  if (!ex_freeze) begin
        else  if (!ex_freeze) begin
                case (id_insn[31:26])           // synopsys parallel_case
                case (id_insn[31:26])           // synopsys parallel_case
 
 
                // j.jal
                // j.jal
                `OR1200_OR32_JAL:
                `OR1200_OR32_JAL:
                        rfwb_op <= #1 `OR1200_RFWBOP_LR;
                        rfwb_op <= #1 {`OR1200_RFWBOP_LR, 1'b1};
 
 
                // j.jalr
                // j.jalr
                `OR1200_OR32_JALR:
                `OR1200_OR32_JALR:
                        rfwb_op <= #1 `OR1200_RFWBOP_LR;
                        rfwb_op <= #1 {`OR1200_RFWBOP_LR, 1'b1};
 
 
                // l.movhi
                // l.movhi
                `OR1200_OR32_MOVHI:
                `OR1200_OR32_MOVHI:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
 
 
                // l.mfspr
                // l.mfspr
                `OR1200_OR32_MFSPR:
                `OR1200_OR32_MFSPR:
                        rfwb_op <= #1 `OR1200_RFWBOP_SPRS;
                        rfwb_op <= #1 {`OR1200_RFWBOP_SPRS, 1'b1};
 
 
                // l.lwz
                // l.lwz
                `OR1200_OR32_LWZ:
                `OR1200_OR32_LWZ:
                        rfwb_op <= #1 `OR1200_RFWBOP_LSU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
 
 
                // l.lbz
                // l.lbz
                `OR1200_OR32_LBZ:
                `OR1200_OR32_LBZ:
                        rfwb_op <= #1 `OR1200_RFWBOP_LSU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
 
 
                // l.lbs
                // l.lbs
                `OR1200_OR32_LBS:
                `OR1200_OR32_LBS:
                        rfwb_op <= #1 `OR1200_RFWBOP_LSU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
 
 
                // l.lhz
                // l.lhz
                `OR1200_OR32_LHZ:
                `OR1200_OR32_LHZ:
                        rfwb_op <= #1 `OR1200_RFWBOP_LSU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
 
 
                // l.lhs
                // l.lhs
                `OR1200_OR32_LHS:
                `OR1200_OR32_LHS:
                        rfwb_op <= #1 `OR1200_RFWBOP_LSU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
 
 
                // l.addi
                // l.addi
                `OR1200_OR32_ADDI:
                `OR1200_OR32_ADDI:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
 
 
                // l.addic
                // l.addic
                `OR1200_OR32_ADDIC:
                `OR1200_OR32_ADDIC:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
 
 
                // l.andi
                // l.andi
                `OR1200_OR32_ANDI:
                `OR1200_OR32_ANDI:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
 
 
                // l.ori
                // l.ori
                `OR1200_OR32_ORI:
                `OR1200_OR32_ORI:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
 
 
                // l.xori
                // l.xori
                `OR1200_OR32_XORI:
                `OR1200_OR32_XORI:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
 
 
                // l.muli
                // l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MULT_IMPLEMENTED
                `OR1200_OR32_MULI:
                `OR1200_OR32_MULI:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
`endif
`endif
 
 
                // Shift and rotate insns with immediate
                // Shift and rotate insns with immediate
                `OR1200_OR32_SH_ROTI:
                `OR1200_OR32_SH_ROTI:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
 
 
                // ALU instructions except the one with immediate
                // ALU instructions except the one with immediate
                `OR1200_OR32_ALU:
                `OR1200_OR32_ALU:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
 
 
`ifdef OR1200_OR32_CUST5
`ifdef OR1200_OR32_CUST5
                // l.cust5 instructions
                // l.cust5 instructions
                `OR1200_OR32_CUST5:
                `OR1200_OR32_CUST5:
                        rfwb_op <= #1 `OR1200_RFWBOP_ALU;
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
`endif
`endif
`ifdef OR1200_FPU_IMPLEMENTED
`ifdef OR1200_FPU_IMPLEMENTED
                  // FPU instructions, lf.XXX.s, except sfxx
                  // FPU instructions, lf.XXX.s, except sfxx
                  `OR1200_OR32_FLOAT:
                  `OR1200_OR32_FLOAT:
                    rfwb_op <= #1 {`OR1200_RFWBOP_FPU,!id_insn[3]};
                    rfwb_op <= #1 {`OR1200_RFWBOP_FPU,!id_insn[3]};

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