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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_fsm.v] - Diff between revs 358 and 364

Rev 358	Rev 364
Line 364...	Line 364...
state <= `OR1200_DCFSM_IDLE;	state <= `OR1200_DCFSM_IDLE;
`addr_r <= 32'b0;`	`addr_r <= 32'b0;`
`hitmiss_eval <= 1'b0;`	`hitmiss_eval <= 1'b0;`
`store <= 1'b0;`	`store <= 1'b0;`
`load <= 1'b0;`	`load <= 1'b0;`
`cnt <= 3'b000;`	`cnt <= 3'd0;`
`cache_miss <= 1'b0;`	`cache_miss <= 1'b0;`
`cache_dirty_needs_writeback <= 1'b0;`	`cache_dirty_needs_writeback <= 1'b0;`
`cache_inhibit <= 1'b0;`	`cache_inhibit <= 1'b0;`
`did_early_load_ack <= 1'b0;`	`did_early_load_ack <= 1'b0;`
`cache_spr_block_flush <= 1'b0;`	`cache_spr_block_flush <= 1'b0;`
Line 451...	Line 451...
`OR1200_DCFSM_LOOP2 : begin // loop/abort	`OR1200_DCFSM_LOOP2 : begin // loop/abort
`if (!dc_en\| biudata_error) begin`	`if (!dc_en\| biudata_error) begin`
state <= `OR1200_DCFSM_IDLE;	state <= `OR1200_DCFSM_IDLE;
`load <= 1'b0;`	`load <= 1'b0;`
`store <= 1'b0;`	`store <= 1'b0;`
`cnt <= 1'b0;`	`cnt <= 3'd0;`
`end`	`end`
`if (biudata_valid & (\|cnt)) begin`	`if (biudata_valid & (\|cnt)) begin`
`cnt <= cnt - 1'b1;`	`cnt <= cnt - 3'd1;`
`addr_r[3:2] <= addr_r[3:2] + 1'b1;`	`addr_r[3:2] <= addr_r[3:2] + 1'b1;`
`end`	`end`
`else if (biudata_valid & !(\|cnt)) begin`	`else if (biudata_valid & !(\|cnt)) begin`
state <= `OR1200_DCFSM_LOOP3;	state <= `OR1200_DCFSM_LOOP3;
`addr_r <= lsu_addr;`	`addr_r <= lsu_addr;`