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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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| Rev 481 |
Rev 846 |
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Line 310... |
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// ACK for when it's a cache miss - load only, is used in MUX for data back
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// ACK for when it's a cache miss - load only, is used in MUX for data back
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// LSU straight off external data bus. In
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// LSU straight off external data bus. In
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// this was is also used for cache inhibit
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// this was is also used for cache inhibit
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// loads.
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// loads.
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assign first_miss_ack = load_miss_ack | load_inhibit_ack;
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// first_hit_ack takes precedence over first_miss_ack
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assign first_miss_ack = ~first_hit_ack & (load_miss_ack | load_inhibit_ack);
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// ACK cache hit on load
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// ACK cache hit on load
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assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
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assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
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hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
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hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
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