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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_fsm.v] - Diff between revs 481 and 846

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Rev 481 Rev 846
Line 310... Line 310...
 
 
   // ACK for when it's a cache miss - load only, is used in MUX for data back
   // ACK for when it's a cache miss - load only, is used in MUX for data back
   //                                  LSU straight off external data bus. In
   //                                  LSU straight off external data bus. In
   //                                  this was is also used for cache inhibit
   //                                  this was is also used for cache inhibit
   //                                  loads.
   //                                  loads.
   assign first_miss_ack = load_miss_ack | load_inhibit_ack;
   // first_hit_ack takes precedence over first_miss_ack
 
   assign first_miss_ack = ~first_hit_ack & (load_miss_ack | load_inhibit_ack);
 
 
   // ACK cache hit on load
   // ACK cache hit on load
   assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
   assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
                         hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
                         hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
 
 

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