| Line 41... |
Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_dc_fsm.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Bugs fixed.
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//
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// Revision 1.9 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.8 2004/04/05 08:29:57 lampret
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// Revision 1.8 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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//
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//
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// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
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// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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// Added embedded memory QMEM.
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| Line 115... |
Line 122... |
clk, rst,
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clk, rst,
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// Internal i/f to top level DC
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// Internal i/f to top level DC
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dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
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dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
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dcram_we, biu_read, biu_write, biu_sel, first_hit_ack, first_miss_ack, first_miss_err,
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burst, tag_we, dc_addr
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burst, tag_we, tag_valid, dc_addr
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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| Line 137... |
Line 144... |
input [31:0] start_addr;
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input [31:0] start_addr;
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output [31:0] saved_addr;
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output [31:0] saved_addr;
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output [3:0] dcram_we;
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output [3:0] dcram_we;
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output biu_read;
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output biu_read;
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output biu_write;
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output biu_write;
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output biu_sel;
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output first_hit_ack;
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output first_hit_ack;
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output first_miss_ack;
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output first_miss_ack;
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output first_miss_err;
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output first_miss_err;
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output burst;
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output burst;
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output tag_we;
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output tag_we;
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output tag_valid;
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output [31:0] dc_addr;
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output [31:0] dc_addr;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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| Line 154... |
Line 163... |
reg [2:0] cnt;
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reg [2:0] cnt;
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reg hitmiss_eval;
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reg hitmiss_eval;
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reg store;
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reg store;
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reg load;
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reg load;
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reg cache_inhibit;
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reg cache_inhibit;
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reg cache_miss;
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//wire tagcomp_miss_wide;
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wire first_store_hit_ack;
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wire first_store_hit_ack;
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//
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//
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// Generate of DCRAM write enables
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// Generate of DCRAM write enables
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//
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//
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assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
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//assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
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assign tag_we = biu_read & biudata_valid & !cache_inhibit;
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assign dcram_we = {4{load & biudata_valid & !cache_inhibit & !hitmiss_eval}} |
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{4{first_store_hit_ack}} & dcqmem_sel_i;
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//assign tag_we = biu_read & biudata_valid & !cache_inhibit;
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assign tag_we = load & (biudata_valid & (!cache_inhibit | !cache_miss) | biudata_error) & !hitmiss_eval |
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store & (biudata_valid & cache_inhibit & !cache_miss | biudata_error) & !hitmiss_eval;
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assign tag_valid = biudata_valid & !cache_inhibit;
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//
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//
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// BIU read and write
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// BIU read and write
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//
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//
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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//assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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assign biu_write = store;
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//assign biu_read = ((hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load)) & (dcqmem_cycstb_i | biudata_valid);
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assign biu_read = (state == `OR1200_DCFSM_CLOAD) & (hitmiss_eval ? ((tagcomp_miss | dcqmem_ci_i) & dcqmem_cycstb_i) : (cache_miss & !cache_inhibit & biudata_valid | dcqmem_cycstb_i & !biudata_error)) |
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(state == `OR1200_DCFSM_LREFILL3) & !(biudata_valid & !cnt) & !biudata_error;
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//assign biu_write = store;
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//assign biu_write = store & dcqmem_cycstb_i;
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assign biu_write = store & dcqmem_cycstb_i;
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assign biu_sel = load;
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assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
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//assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
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assign dc_addr = (!(load | store) | hitmiss_eval) ? start_addr : saved_addr;
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assign saved_addr = saved_addr_r;
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assign saved_addr = saved_addr_r;
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//
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//
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// Assert for cache hit first word ready
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// Assert for cache hit first word ready
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// Assert for store cache hit first word ready
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// Assert for store cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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// Assert for cache miss first word stored/loaded with an error
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//
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//
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assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
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//assign tagcomp_miss_wide = tagcomp_miss | (saved_addr != start_addr);
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assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
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//assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss_wide & !cache_inhibit | first_store_hit_ack;
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assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i | first_store_hit_ack;
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//assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss_wide & biudata_valid & !cache_inhibit;
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assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !hitmiss_eval & !cache_miss & biudata_valid & !cache_inhibit;
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assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
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assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
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assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
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assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
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//
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//
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// Assert burst when doing reload of complete cache line
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// Assert burst when doing reload of complete cache line
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//
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//
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assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
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//assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
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| (state == `OR1200_DCFSM_LREFILL3)
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// | (state == `OR1200_DCFSM_LREFILL3)
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`ifdef OR1200_DC_STORE_REFILL
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//`ifdef OR1200_DC_STORE_REFILL
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| (state == `OR1200_DCFSM_SREFILL4)
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// | (state == `OR1200_DCFSM_SREFILL4)
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`endif
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//`endif
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;
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// ;
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assign burst = load & (hitmiss_eval ? !dcqmem_ci_i : !cache_inhibit);
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//
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//
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// Main DC FSM
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// Main DC FSM
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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| Line 203... |
Line 230... |
saved_addr_r <= #1 32'b0;
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saved_addr_r <= #1 32'b0;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cnt <= #1 3'b000;
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cnt <= #1 3'b000;
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cache_miss <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else
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else
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case (state) // synopsys parallel_case
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case (state) // synopsys parallel_case
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`OR1200_DCFSM_IDLE :
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`OR1200_DCFSM_IDLE : begin
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if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin // store
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if (dcqmem_we_i & dc_en & dcqmem_cycstb_i) // store
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state <= #1 `OR1200_DCFSM_CSTORE;
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state <= #1 `OR1200_DCFSM_CSTORE;
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saved_addr_r <= #1 start_addr;
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else if (!dcqmem_we_i & dc_en & dcqmem_cycstb_i) // store
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hitmiss_eval <= #1 1'b1;
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store <= #1 1'b1;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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else if (dc_en & dcqmem_cycstb_i) begin // load
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state <= #1 `OR1200_DCFSM_CLOAD;
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state <= #1 `OR1200_DCFSM_CLOAD;
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saved_addr_r <= #1 start_addr;
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cache_inhibit <= #1 1'b0; // not dcqmem_ci_i because it is delayed (due to DTLB)
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 dc_en & dcqmem_cycstb_i ;
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store <= #1 1'b0;
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store <= #1 dc_en & dcqmem_cycstb_i & dcqmem_we_i;
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load <= #1 1'b1;
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load <= #1 dc_en & dcqmem_cycstb_i & !dcqmem_we_i;
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cache_inhibit <= #1 1'b0;
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end
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else begin // idle
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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`OR1200_DCFSM_CLOAD: begin // load
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`OR1200_DCFSM_CLOAD: begin // load
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if (dcqmem_cycstb_i & dcqmem_ci_i)
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if (!hitmiss_eval && cache_miss && !cache_inhibit && biudata_valid) begin
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cache_inhibit <= #1 1'b1;
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if (hitmiss_eval)
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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if ((hitmiss_eval & !dcqmem_cycstb_i) || // load aborted (usually caused by DMMU)
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(biudata_error) || // load terminated with an error
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((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // load from cache-inhibited area
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
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state <= #1 `OR1200_DCFSM_LREFILL3;
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state <= #1 `OR1200_DCFSM_LREFILL3;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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hitmiss_eval <= #1 1'b0;
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cnt <= #1 `OR1200_DCLS-2;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (!tagcomp_miss & !dcqmem_ci_i) begin // load hit, finish immediately
|
else if (!dcqmem_cycstb_i || !hitmiss_eval && (biudata_valid || biudata_error) || hitmiss_eval && !tagcomp_miss && !dcqmem_ci_i) begin
|
state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else // load in-progress
|
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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cnt <= #1 `OR1200_DCLS-2;
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if (hitmiss_eval) begin
|
|
cache_inhibit <= #1 dcqmem_ci_i;
|
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cache_miss <= #1 tagcomp_miss;
|
end
|
end
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`OR1200_DCFSM_LREFILL3 : begin
|
if (hitmiss_eval)
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
saved_addr_r <= #1 start_addr;
|
cnt <= #1 cnt - 3'd1;
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else if (biudata_valid)
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;
|
end
|
end
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else if (biudata_valid) begin // last load of line refill
|
`OR1200_DCFSM_LREFILL3 : begin
|
|
if (!dc_en || biudata_valid && !cnt || biudata_error) begin // finish/abort
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
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load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
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if (biudata_valid) begin
|
|
cnt <= #1 cnt - 1'b1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;
|
|
end
|
end
|
end
|
`OR1200_DCFSM_CSTORE: begin // store
|
`OR1200_DCFSM_CSTORE: begin // store
|
if (dcqmem_cycstb_i & dcqmem_ci_i)
|
hitmiss_eval <= 1'b0;
|
cache_inhibit <= #1 1'b1;
|
if (hitmiss_eval) begin
|
if (hitmiss_eval)
|
cache_inhibit <= #1 dcqmem_ci_i;
|
saved_addr_r[31:13] <= #1 start_addr[31:13];
|
cache_miss <= #1 tagcomp_miss;
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if ((hitmiss_eval & !dcqmem_cycstb_i) || // store aborted (usually caused by DMMU)
|
|
(biudata_error) || // store terminated with an error
|
|
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // store to cache-inhibited area
|
|
state <= #1 `OR1200_DCFSM_IDLE;
|
|
hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
|
|
end
|
end
|
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if (hitmiss_eval)
|
|
saved_addr_r <= #1 start_addr;
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and doq load refill
|
else if (biudata_valid)
|
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;
|
|
cnt <= #1 `OR1200_DCLS-1;
|
|
if (!hitmiss_eval && cache_miss && !cache_inhibit && biudata_valid) begin
|
state <= #1 `OR1200_DCFSM_SREFILL4;
|
state <= #1 `OR1200_DCFSM_SREFILL4;
|
hitmiss_eval <= #1 1'b0;
|
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
load <= #1 1'b1;
|
load <= #1 1'b1;
|
cnt <= #1 `OR1200_DCLS-1;
|
|
cache_inhibit <= #1 1'b0;
|
|
end
|
end
|
|
else
|
`endif
|
`endif
|
else if (biudata_valid) begin // store hit, finish write-through
|
if (!dcqmem_cycstb_i || !hitmiss_eval && (biudata_error || biudata_valid)) begin
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
hitmiss_eval <= #1 1'b0;
|
|
store <= #1 1'b0;
|
store <= #1 1'b0;
|
cache_inhibit <= #1 1'b0;
|
|
end
|
|
else // store write-through in-progress
|
|
hitmiss_eval <= #1 1'b0;
|
|
end
|
end
|
`ifdef OR1200_DC_STORE_REFILL
|
`ifdef OR1200_DC_STORE_REFILL
|
`OR1200_DCFSM_SREFILL4 : begin
|
`OR1200_DCFSM_SREFILL4 : begin
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
if (!dc_en) begin // somebody just turned off DC therefore we abort
|
|
cnt <= #1 3'd0; // DC will have to be invalidated before
|
|
state <= #1 `OR1200_DCFSM_IDLE; // it can be turned on again
|
|
load <= #1 1'b0;
|
|
end
|
|
else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 1'd1;
|
cnt <= #1 cnt - 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
|
end
|
end
|
else if (biudata_valid) begin // last load of line refill
|
else if (biudata_valid) begin // last load of line refill
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
load <= #1 1'b0;
|
load <= #1 1'b0;
|
end
|
end
|
end
|
|
`endif
|
`endif
|
|
end
|
|
|
default:
|
default:
|
state <= #1 `OR1200_DCFSM_IDLE;
|
state <= #1 `OR1200_DCFSM_IDLE;
|
endcase
|
endcase
|
end
|
end
|
|
|
